本文關(guān)鍵詞：VHDL數(shù)字電路設(shè)計教程，由筆耕文化傳播整理發(fā)布。

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第 5 章習題參考答案
Problem 5.1 library ieee; use ieee.std_logic_1164.all; package my_data_type is constant m: integer :=8; type vector_array is array (n

atural range<>) of std_logic_vector(m-1 downto 0); end my_data_type; library ieee; use ieee.std_logic_1164.all; use work.my_data_type.all; entity n_mux is generic (n: integer :=8); port( datain: in vector_array(0 to n-1) ; sel: in integer range 0 to n-1; dataout: out std_logic_vector( m-1 downto 0)); end; architecture bhv of n_mux is begin dataout<=datain(sel);

end; Problem 5.2 方法一： 方法一：利用簡單賦值語句設(shè)計 library ieee; use ieee.std_logic_1164.all; entity priority_encoder is port(x:in std_logic_vector(7 downto 1); y:out std_logic_vector(2 downto 0)); end; architecture bhv of priority_encoder is begin y(2)<=x(7) or x(6) or x(5) or x(4); y(1)<=x(7) or x(6) or (( not x(5) and not x(4)) and (x(3) or x(2))); y(0)<=x(7) or (not x(6) and (x(5) or (not x(4) and (x(3) or (not x(2) and x(1)))))); end; 方法二：利用 WHEN 語句設(shè)計 方法二： library ieee; use ieee.std_logic_1164.all; entity priority_encoder is port(x:in std_logic_vector(7 downto 1); y:out std_logic_vector(2 downto 0));

end; architecture bhv of priority_encoder is begin y<="111" when x(7)='1' else "110" when x(6)='1' else "101" when x(5)='1' else "100" when x(4)='1' else "011" when x(3)='1' else "010" when x(2)='1' else "001" when x(1)='1' else "000"; end; Problem 5.4 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder8 is port(a,b:in std_logic_vector(7 downto 0); cin:in std_logic; sum:out std_logic_vector(7 downto 0); cout:out std_logic); end;

architecture bhv of adder8 is signal a0,b0,cin0, s:std_logic_vector(8 downto 0); begin a0<='0'&a; b0<='0'&b; cin0<="00000000"&cin; s<=a0+b0+cin0; sum<=s(7 downto 0); cout<=s(8); end; Problem5.5 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_signed.all; entity add_sub is port(a,b:in unsigned(7 downto 0); sel:in bit_vector(1 downto 0); sum:out std_logic_vector(8 downto 0)); end; architecture bhv of add_sub is signal temp1,temp2:unsigned (8 downto 0); signal temp3,temp4:signed(8 downto 0);

--signal an,as,sn,ss:std_logic_vector(8 downto 0); signal a0,b0:signed (7 downto 0); signal cin0:std_logic_vector(7 downto 0); begin a0<=conv_signed(a,8); b0<=conv_signed(b,8); temp1<=conv_unsigned((a+b),9); temp2<=conv_unsigned((a-b),9); temp3<=conv_signed((a0+b0),9); temp4<=conv_signed((a0-b0),9); sum<=conv_std_logic_vector(temp1,9)when sel="00" else conv_std_logic_vector(temp3,9)when sel="01" else conv_std_logic_vector(temp2,9)when sel="10" else conv_std_logic_vector(temp4,9); end; Problem 5.6 library ieee; use ieee.std_logic_1164.all; entity gray_encoder is generic(n: integer:=4) ; port(input:in std_logic_vector(n-1 downto 0); output:out std_logic_vector(n-1 downto 0));

end; architecture bhv of gray_encoder is begin output(n-1)<=input(n-1); output(n-2 downto 0)<=input(n-2 downto 0) xor input(n-1 downto 1); end;

Problem 5.7 將原題修改后的作業(yè)題， （ 要求能夠?qū)崿F(xiàn)連續(xù)移位， shift 當 信號為 0 時，保持不變，否則每次左移移位，最低位補 0，直到全 0 為止。 ） library ieee; use ieee.std_logic_1164.all; entity barrel_shifter is port(inp:in std_logic_vector(7 downto 0); shift: in bit; sel:in integer range 0 to 7; outp:out std_logic_vector(7 downto 0)); end; architecture bhv of barrel_shifter is type matrix is array(7 downto 0) of std_logic_vector (7 downto 0); signal row: matrix;

begin row(0)<=inp; l1:for i in 1 to 7 generate row(i)<=row(0) when shift='0' else row(i-1)(6 downto 0)&'0' ; end generate; outp<=row(sel); end; Problem 5.8 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity comp is port(a,b:in integer range 0 to 255; sel:in std_logic; x1,x2,x3:out std_logic); end; architecture bhv of comp is signal a_signed, b_signed: signed(7 downto 0); signal temp: std_logic_vector (1 to 4); begin a_signed<=conv_signed(a,8);

b_signed<=conv_signed(b,8); temp(1)<='1' when a>b else '0'; temp(2)<='1' when a=b else '0'; temp(3)<='1' when a_signed>b_signed else '0'; temp(4)<='1' when a_signed=b_signed else '0'; x1<=temp(1) when sel='0' else temp(3); x2<=temp(2) when sel='0' else temp(4); x3<=not(temp(1) or temp(2)) when sel='0' else not(temp(3) or temp(4)); end;



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  本文關(guān)鍵詞：VHDL數(shù)字電路設(shè)計教程，，由筆耕文化傳播整理發(fā)布。