本文選題：可重構(gòu)計(jì)算　切入點(diǎn)：可重構(gòu)編譯　出處：《哈爾濱工程大學(xué)》2016年博士論文　論文類型：學(xué)位論文

【摘要】：隨著半導(dǎo)體技術(shù)的發(fā)展,基于時(shí)間-空間多維計(jì)算方式的可重構(gòu)計(jì)算體系結(jié)構(gòu),突破了馮.諾依曼結(jié)構(gòu)的局限性,兼具專用集成電路芯片ASIC高效性與通用處理器靈活性的可重構(gòu)計(jì)算在高性能計(jì)算、數(shù)字信號(hào)處理、網(wǎng)絡(luò)信息安全等重要領(lǐng)域中被廣泛應(yīng)用,在商業(yè)上和技術(shù)上存在的潛在價(jià)值逐漸被人們重視,成為另一種主流計(jì)算方式。對(duì)于通用計(jì)算領(lǐng)域來說,基于GPP+FPGA異構(gòu)架構(gòu)的可重構(gòu)計(jì)算架構(gòu)在能耗、存儲(chǔ)、性能等多方面均優(yōu)于傳統(tǒng)架構(gòu)的通用處理器,這使得可重構(gòu)計(jì)算成為未來新型計(jì)算的一個(gè)重要研究方向。由于面向通用計(jì)算領(lǐng)域的可重構(gòu)計(jì)算相關(guān)研究均處于起步階段,雖然已經(jīng)取得了很多研究成果,但仍存在很多問題亟需深入研究。影響可重構(gòu)計(jì)算系統(tǒng)實(shí)際推廣效果的一個(gè)重要因素是相關(guān)軟件生態(tài)系統(tǒng)不成熟,同時(shí)不受半導(dǎo)體制造工藝和相關(guān)硬件技術(shù)的限制,使得面向可重構(gòu)計(jì)算系統(tǒng)的可重構(gòu)編譯器相關(guān)技術(shù)成為目前世界范圍內(nèi)的研究重點(diǎn)與熱點(diǎn)。通過對(duì)可重構(gòu)計(jì)算系統(tǒng)實(shí)現(xiàn)通用計(jì)算領(lǐng)域中應(yīng)用程序硬件加速的過程進(jìn)行分析,改善可重構(gòu)編譯器實(shí)現(xiàn)應(yīng)用程序中循環(huán)結(jié)構(gòu)到可重構(gòu)計(jì)算系統(tǒng)平臺(tái)并行流水硬件加速單元的自動(dòng)映射技術(shù)成為當(dāng)前該領(lǐng)域關(guān)注的課題。在前人工作的基礎(chǔ)上,本文主要針對(duì)循環(huán)程序中的運(yùn)算單元、控制單元、存儲(chǔ)單元三個(gè)主要功能模塊的自動(dòng)映射及優(yōu)化技術(shù)展開深入研究,具體研究內(nèi)容如下:(1)在現(xiàn)有可重構(gòu)編譯器實(shí)現(xiàn)循環(huán)程序到流水執(zhí)行的運(yùn)算單元自動(dòng)映射過程中,往往采用流水線直接劃分方法,沒有考慮基本運(yùn)算指令在FPGA上執(zhí)行時(shí)真實(shí)的硬件延時(shí)特性,導(dǎo)致流水線劃分結(jié)果不優(yōu)。針對(duì)這種情況,本文設(shè)計(jì)了一種基于硬件延時(shí)特性的流水線自動(dòng)劃分算法。結(jié)合循環(huán)程序在FPGA上運(yùn)行時(shí)基本運(yùn)算指令的硬件延時(shí)特性,建立基本指令硬件延時(shí)特征庫,并以基本運(yùn)算指令延時(shí)為權(quán)值,進(jìn)行流水線合并和優(yōu)化,實(shí)現(xiàn)流水線的自動(dòng)劃分。實(shí)驗(yàn)結(jié)果表明,該算法能夠有效降低流水線劃分段數(shù),從而減少了因流水線劃分所導(dǎo)致的硬件資源開銷,同時(shí)降低了運(yùn)算單元單次迭代執(zhí)行時(shí)的時(shí)鐘周期個(gè)數(shù)。(2)在現(xiàn)有可重構(gòu)編譯器中,循環(huán)程序流水執(zhí)行時(shí)迭代間啟動(dòng)間距均采用制導(dǎo)語句指令方式控制,但是該方式只能生成固定的迭代間啟動(dòng)間距信息,不能充分提高循環(huán)程序流水執(zhí)行性能,同時(shí)限制了可重構(gòu)編譯器的自動(dòng)化水平。針對(duì)該問題,本文設(shè)計(jì)了一種循環(huán)流水迭代間啟動(dòng)間距自動(dòng)分析及優(yōu)化方法。通過建立循環(huán)流水迭代間啟動(dòng)間距信息模型,采用循環(huán)流水迭代間非固定啟動(dòng)間距控制策略,完成循環(huán)流水迭代間啟動(dòng)間距的自動(dòng)分析,同時(shí)采用流水線調(diào)度技術(shù)對(duì)迭代間啟動(dòng)間距進(jìn)行優(yōu)化。實(shí)驗(yàn)結(jié)果表明,本文所設(shè)計(jì)的循環(huán)流水迭代間非固定啟動(dòng)間距控制策略,能夠有效減少循環(huán)程序流水執(zhí)行時(shí)迭代間等待延時(shí)時(shí)間,同時(shí)采用自動(dòng)分析算法能夠有效提高可重構(gòu)編譯器的自動(dòng)化水平。(3)在可重構(gòu)計(jì)算系統(tǒng)中目前已經(jīng)存在很多并行存儲(chǔ)結(jié)構(gòu)的研究成果,為了提高數(shù)據(jù)訪問的并行性和重用性,往往采用空間換時(shí)間的策略,但是,在資源開銷與性能方面均有提高的空間。針對(duì)這種情況,本文設(shè)計(jì)了一種參數(shù)化并行存儲(chǔ)結(jié)構(gòu)自動(dòng)映射方法。針對(duì)類仿射型數(shù)組下標(biāo)應(yīng)用,設(shè)計(jì)一種參數(shù)化并行存儲(chǔ)體系結(jié)構(gòu),通過自動(dòng)生成算法構(gòu)建循環(huán)程序的訪存數(shù)據(jù)依賴圖,并進(jìn)行并行存儲(chǔ)結(jié)構(gòu)模板的參數(shù)計(jì)算,在可重構(gòu)編譯器中實(shí)現(xiàn)并行存儲(chǔ)體系結(jié)構(gòu)的自動(dòng)映射生成。實(shí)驗(yàn)結(jié)果表明,該存儲(chǔ)體系結(jié)構(gòu)能夠充分挖掘循環(huán)中的數(shù)據(jù)并行性和重用性,與現(xiàn)有方案相比,能夠在占用較少硬件資源的情況下,提升循環(huán)程序流水執(zhí)行的性能。最后,本文結(jié)合上述研究內(nèi)容,分別將基于硬件延時(shí)特性的流水線自動(dòng)劃分算法、循環(huán)流水迭代間啟動(dòng)間距自動(dòng)分析及優(yōu)化方法、參數(shù)化并行存儲(chǔ)結(jié)構(gòu)自動(dòng)映射方法等技術(shù)應(yīng)用在循環(huán)程序運(yùn)算單元、控制單元、存儲(chǔ)單元的自動(dòng)生成過程中,構(gòu)建一種面向可重構(gòu)編譯器的循環(huán)流水自動(dòng)映射框架。實(shí)驗(yàn)結(jié)果表明,本文方法在提高可重構(gòu)編譯器自動(dòng)化水平的同時(shí),能夠有效提高循環(huán)程序在可重構(gòu)計(jì)算系統(tǒng)中流水執(zhí)行的性能,具有一定的可行性。
[Abstract]:With the development of semiconductor technology, time - space multidimensional calculation based on the reconstruction of the way to calculate system structure, break the limitation of the structure of von Neumann, reconstruction of both ASIC ASIC efficiency and flexibility of general purpose processor can be calculated in high performance computing, digital signal processing, has been widely used in the important field of network and information security etc. in the potential value in business and technology has been gradually valued, become a mainstream computing. For general-purpose computing, computing architecture in energy consumption, storage reconstruction of GPP+FPGA heterogeneous architecture based on general purpose processor, performance and other aspects are better than that of traditional architecture, which makes reconfigurable computing has become a a new important research direction in the future of computing. As for general-purpose reconstruction field calculation related studies are in the initial stage, although it has been taken Got a lot of achievements, but there are still many problems need to be further study. Reconfigurable computing is one of the important factors to promote the effect of the actual system is related to the software ecosystem is not mature, and not by the semiconductor manufacturing process and related hardware technology, makes for reconfigurable computing system reconfigurable Compiler Techniques become the world the emphases of research. Through the process analysis of reconfigurable computing system to achieve universal computing hardware accelerated applications, improve the reconfigurable compiler application cycle structure to automatically mapping technology of reconfigurable computing system platform parallel hardware acceleration unit has become the field of attention. Based on previous work on the operation unit, cycling program control unit, three main power storage unit An in-depth study on the automatic mapping and optimization module, the specific contents are as follows: (1) in the existing operation unit automatic mapping process reconstruction compiler implementation program to the implementation of the water cycle, often by direct division method of pipeline, without considering the basic operation instruction execution characteristics of real hardware delay in FPGA, leading to pipeline the division result is not optimal. In view of this situation, this paper designed a kind of automatic partitioning algorithm based on pipelined hardware delay characteristics. Combined with the hardware delay cycle program is run on FPGA basic operation instruction, establish the basic instruction hardware delay feature library, and to basic arithmetic instructions for delay weights of the pipelined merger and optimization automatic division of the realization of the pipeline. The experimental results show that this algorithm can effectively reduce the pipeline partition number, so as to reduce the pipeline partition The hardware resources which, while reducing the operation unit of a single iteration execution when the number of clock cycles. (2) in the existing reconfigurable compiler, water cycle program execution start between space using iterative guidance statement instruction mode control, but this method can only generate fixed spacing between iterations starting information, not to fully enhance the water cycle program execution performance, while limiting the automation level of the reconfigurable compiler. Aiming at this problem, this paper designs a recirculating iteration and optimization method of automatic analysis between the start distance. Distance through information model started to establish a recirculating iteration, by circulating water between the non fixed iteration initiation interval control strategy automatically analysis of circulating water and the spacing between iterations starting, the iteration between initiation interval was optimized by the pipeline scheduling technique. Experimental results show that the, The design of the water cycle iterative non fixed pitch control strategy can effectively reduce the cycle delay time for pipelined execution between iterations, and the automatic analysis algorithm can effectively improve the automation level of the reconfigurable compiler. (3) in the reconfigurable computing system has many parallel storage structure of the research results. In order to improve the reusability of parallelism and data access, often using the strategy space for time, but improves the resource overhead and performance space. In view of this situation, this paper designs a parametric parallel mapping method. According to the structure of the automatic storage class of affine array subscript applications, a parametric parallel design storage architecture, construction cycle program through the automatic generation algorithm of memory data dependence graph, and the parameter calculation of parallel storage structure template, In the parallel implementation of automatic map generation storage architecture reconstruction compiler. The experimental results show that the storage architecture can fully exploit the parallelism and reuse cycle data, compared with the existing schemes can occupy less hardware resources, and improve the performance up cycle pipelining. Finally, combining with the the above research contents, respectively, automatic partitioning algorithm hardware delay characteristics of pipeline based on recirculating iteration and optimization method of automatic start between the analysis of space, application of parametric parallel storage structure automatic mapping method of technology control unit in cycle operation unit, automatic generation of storage unit in the construction of a reconfigurable compiler circulating water automatic mapping framework. The experimental results show that this method can improve the level of automation in the reconstruction of the compiler at the same time, can effectively It is feasible to improve the performance of the circulation program in the reconfigurable computing system.

【學(xué)位授予單位】：哈爾濱工程大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類號(hào)】：TP314

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