本文選題：延時電路 + 延時鎖定環(huán)�。� 參考：《東南大學(xué)》2017年碩士論文

【摘要】：隨著高速混合信號電路的發(fā)展,信號的時序?qū)φw系統(tǒng)日漸產(chǎn)生著至關(guān)重要的影響。因此,設(shè)計電路時常需要添加若干延時單元,用于產(chǎn)生或補償路徑間的延時差異,以實現(xiàn)特定的性能要求。延時電路應(yīng)用廣泛,除了可以補償不同信號鏈路間的延時差,還可以運用于寬帶波束形成系統(tǒng)電路、有限沖激響應(yīng)(FIR)濾波器、無限沖激響應(yīng)(IIR)濾波器以及均衡器電路的設(shè)計中。因此,研究和設(shè)計高性能的延時電路具有重要的價值和意義。本文采用IBM 0.13μm SiGe BiCMOS工藝設(shè)計了有源延時電路和延時鎖定環(huán)路。本文在介紹延時電路基本原理和比較各種延時電路結(jié)構(gòu)的基礎(chǔ)上采用了 gm-C結(jié)構(gòu)的有源延時電路,并使用高性能的SiGeHBT管作為輸入管,提高了延時電路的工作頻帶范圍。延時電路通過調(diào)節(jié)可變電容改變延時時間,并利用電感峰化和射極負反饋技術(shù)拓展電路帶寬。為了減少信號在輸入輸出端口的反射,設(shè)計的匹配電路可以保證延時電路在工作頻帶內(nèi)反射系數(shù)小于-10dB。本文中的延時鎖定環(huán)路可以調(diào)節(jié)延時電路的延時時間,使其在不同工藝角、溫度和電壓下的延時時間不變。延時鎖定環(huán)路由延時電路、乘法器和V/I轉(zhuǎn)換器電路組成。延時鎖定環(huán)路具有負反饋調(diào)節(jié)功能,可以保證環(huán)路中的延時電路總延時為四分之一的時鐘周期。為了減少了環(huán)路中各模塊引入的相位誤差,設(shè)計了全對稱的四象限乘法器和低失調(diào)V/I轉(zhuǎn)換器,可以有效提高延時鎖定環(huán)路的鎖定精度。設(shè)計完成的芯片尺寸為500μm×800μm,測試結(jié)果顯示,在4-12GHz的工作頻率范圍內(nèi),單級延時電路的平均延時時間可以保持在8ps左右,當(dāng)控制電壓變化時,單級延時電路的延時時間可以從7.3ps變化到8.4ps。在延時電路的輸入輸出端加入的匹配電路,可以保證電路的S11和S22反射系數(shù)在0.2-25GHz內(nèi)小于-10dB。當(dāng)改變時鐘信號頻率時,延時鎖定環(huán)路產(chǎn)生的控制電壓可以調(diào)節(jié)延時電路的延時時間,并提高延時電路延時的穩(wěn)定性。本文延時單元與延時鎖定環(huán)路的設(shè)計,對今后低延時寬頻帶延時電路的設(shè)計和應(yīng)用具有一定的意義。
[Abstract]:With the development of high speed mixed signal circuit, the timing of the signal is becoming more and more important to the whole system. Therefore, it is often necessary to add a number of delay elements to the circuit to generate or compensate for delay differences between paths in order to achieve specific performance requirements. Delay circuits are widely used in the design of wideband beamforming system circuits, finite impulse response (FIR) filters, infinite impulse response (IIR) filters and equalizer circuits in addition to compensating for delay differences between different signal links. Therefore, the research and design of high performance delay circuit has important value and significance. In this paper, the active delay circuit and delay locking loop are designed using IBM 0.13 渭 m SiGe BiCMOS technology. Based on the introduction of the basic principle of delay circuit and the comparison of various delay circuit structures, the active delay circuit with gm-C structure is adopted in this paper, and the high performance SiGeHBT transistor is used as input tube, which improves the working frequency range of delay circuit. The delay circuit changes the delay time by adjusting the variable capacitance, and extends the circuit bandwidth by using the inductance peaking and emitter negative feedback technology. In order to reduce the reflection of the signal at the input and output ports, the designed matching circuit can ensure that the reflection coefficient of the delay circuit is less than -10 dB in the working frequency band. The delay locking loop in this paper can adjust the delay time of the delay circuit and keep the delay time constant at different processing angles, temperatures and voltages. The delay locking loop consists of a delay circuit, a multiplier and a V / I converter. The delay locking loop has the function of negative feedback regulation, which can guarantee the total delay time of the delay circuit to be 1/4 clock cycle in the loop. In order to reduce the phase error introduced by each module in the loop, an all-symmetric four-quadrant multiplier and a low-offset V / P I converter are designed, which can effectively improve the locking accuracy of the delay locking loop. The size of the designed chip is 500 渭 m 脳 800 渭 m. The test results show that the average delay time of single-stage delay circuit can be kept around 8ps within the operating frequency range of 4-12GHz, and when the control voltage changes, The delay time of single stage delay circuit can be changed from 7.3ps to 8.4 ps. A matching circuit is added to the input and output of the delay circuit to ensure that the reflection coefficients of S11 and S22 are less than -10 dB in 0.2-25GHz. When the frequency of the clock signal is changed, the control voltage generated by the delay locking loop can adjust the delay time of the delay circuit and improve the delay stability of the delay circuit. The design of delay cell and delay locking loop in this paper is of great significance to the design and application of low delay broadband delay circuit in the future.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN432

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相關(guān)期刊論文 前1條

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本文編號：1941825