本文選題：人臉檢測(cè) + FPGA　； 參考：《上海交通大學(xué)》2008年碩士論文

【摘要】： 人臉識(shí)別技術(shù)繼指紋識(shí)別、虹膜識(shí)別以及聲音識(shí)別等生物識(shí)別技術(shù)之后,以其獨(dú)特的方便、經(jīng)濟(jì)及準(zhǔn)確性而越來越受到世人的矚目。作為人臉識(shí)別系統(tǒng)的重要環(huán)節(jié)—人臉檢測(cè),隨著研究的深入和應(yīng)用的擴(kuò)大,在視頻會(huì)議、圖像檢索、出入口控制以及智能人機(jī)交互等領(lǐng)域有著重要的應(yīng)用前景,發(fā)展速度異常迅猛。 FPGA的制造技術(shù)不斷發(fā)展,它的功能、應(yīng)用和可靠性逐漸增加,在各個(gè)行業(yè)也顯現(xiàn)出自身的優(yōu)勢(shì)。FPGA允許用戶根據(jù)自己的需要來建立自己的模塊,為用戶的升級(jí)和改進(jìn)留下廣闊的空間。并且速度更高,密度也更大,其設(shè)計(jì)方法的靈活性降低了整個(gè)系統(tǒng)的開發(fā)成本,FPGA設(shè)計(jì)成為電子自動(dòng)化設(shè)計(jì)行業(yè)不可缺少的方法。 本文從人臉檢測(cè)算法入手,總結(jié)基于FPGA上的嵌入式系統(tǒng)設(shè)計(jì)方法,使用IBM的Coreconnect掛接自定義模塊技術(shù)。經(jīng)過訓(xùn)練分類器、定點(diǎn)化、以及硬件加速等方法后,能夠使人臉檢測(cè)系統(tǒng)在基于Xilinx的Virtex II Pro開發(fā)板上平臺(tái)上,達(dá)到實(shí)時(shí)的檢測(cè)效果。本文工作和成果可以具體描述如下: 1.算法分析:對(duì)于人臉檢測(cè)算法,首先確保的是檢測(cè)率的準(zhǔn)確性程度。本文所采用的是基于Paul Viola和Michael J.Jones提出的一種基于Adaboost算法的人臉檢測(cè)方法。算法中較多的是積分圖的特征值計(jì)算,這便于進(jìn)一步的硬件設(shè)計(jì)。同時(shí)對(duì)檢測(cè)算法進(jìn)行耗時(shí)分析確定運(yùn)行速度的瓶頸。 2.軟硬件功能劃分:這一步考慮市場(chǎng)可以提供的資源狀況,又要考慮系統(tǒng)成本、開發(fā)時(shí)間等諸多因素。Xilinx公司提供的Virtex II Pro開發(fā)板,在上面有可以供利用的Power PC處理器、可擴(kuò)展的存儲(chǔ)器、I/O接口、總線及數(shù)據(jù)通道等,通過分析可以對(duì)算法進(jìn)行細(xì)致的劃分,實(shí)現(xiàn)需要加速的模塊。 3.定點(diǎn)化:在Adaboost算法中,需要進(jìn)行大量的浮點(diǎn)計(jì)算。這里采用的方法是直接對(duì)數(shù)據(jù)位進(jìn)行操作它提取指數(shù)和尾數(shù),然后對(duì)尾數(shù)執(zhí)行移位操作。 4.改進(jìn)檢測(cè)用的級(jí)聯(lián)分類器的訓(xùn)練,提出可以迅速提高分類能力、特征數(shù)量大大減小的一種訓(xùn)練方法。 5.最后對(duì)系統(tǒng)的整體進(jìn)行了驗(yàn)證。實(shí)驗(yàn)表明,在視頻輸入輸出接入的同時(shí),人臉檢測(cè)能夠達(dá)到17fps的檢測(cè)速度,并且獲得了很好的檢測(cè)率以及較低的誤檢率。
[Abstract]:Face recognition technology, after biometric identification, iris recognition and sound recognition, has attracted more and more attention with its unique convenience, economy and accuracy. As an important part of face recognition system, face detection, with the deepening of research and application, video conferencing, image retrieval, and entrance Control and intelligent human-machine interaction and other fields have important application prospects, and the speed of development is extremely fast.
The manufacturing technology of FPGA continues to develop, its function, application and reliability have gradually increased, and its advantages in various industries are also showing its own advantages.FPGA allows users to build their own modules according to their needs and leave wide space for the user's upgrading and improvement. And the speed is higher, the density is greater, and the flexibility of its design method is reduced. The development cost of the whole system, FPGA design has become an indispensable method in the electronic automation design industry.
This paper starts with the face detection algorithm, summarizes the design method of embedded system based on FPGA, and uses the Coreconnect connection custom module technology of IBM. After training classifier, fixed-point, and hardware acceleration, it can make the face detection system on the Xilinx based Virtex II Pro development board platform to achieve real-time detection. The work and achievements can be described in detail as follows:
1. algorithm analysis: for the face detection algorithm, the first one is to ensure the accuracy of the detection rate. In this paper, a face detection method based on the Adaboost algorithm based on Paul Viola and Michael J.Jones is adopted. The algorithm is more important for the calculation of the eigenvalue of the integral graph, which is convenient for further hardware design. The method is used for time consuming analysis to determine the bottleneck of the running speed.
2. software and hardware function division: this step takes into consideration the resource situation that the market can provide, but also consider the Virtex II Pro development board provided by.Xilinx company, such as system cost, development time, and so on. There are Power PC processor, extensible memory, I/O interface, bus and data channel which can be used, and can be calculated by analysis. The method is meticulously divided to realize modules that need acceleration.
3. fixed-point: in the Adaboost algorithm, a large number of floating-point calculations are required. The method used here is to operate the data bit directly, extract the index and the end, and then perform the shift operation on the tail number.
4. improve the training of cascade classifier for detection, and propose a training method that can quickly improve classification ability and reduce the number of features greatly.
5. finally, the whole system is verified. The experiment shows that, while the video input and output are connected, the face detection can reach the detection speed of 17fps, and the detection rate is very good and the false detection rate is low.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2008
【分類號(hào)】：TP391.41;TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

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本文編號(hào)：1930115