本文選題：陣列天線 + 互耦��； 參考：《南京理工大學(xué)》2017年碩士論文

【摘要】：復(fù)雜電磁環(huán)境下的快速目標(biāo)檢測(cè)和跟蹤已經(jīng)成為未來雷達(dá)系統(tǒng)研制和裝備必須考慮的核心技術(shù)之一,數(shù)字陣列雷達(dá)采用自適應(yīng)波束形成技術(shù),可以有效抑制空域強(qiáng)干擾。本文主要針對(duì)數(shù)字陣列雷達(dá)存在旁瓣和主瓣干擾情況下快速、精確的目標(biāo)角度估計(jì)的需要,完成了陣列天線建模和四通道快速自適應(yīng)單脈沖算法研究,進(jìn)而針對(duì)某二維數(shù)字陣列雷達(dá)的實(shí)際要求,研制了96通道中頻采樣數(shù)字波束形成電路硬件平臺(tái),完成了硬件電路調(diào)試測(cè)試,根據(jù)系統(tǒng)的多模式工作要求完成了采用四通道自適應(yīng)單脈沖技術(shù)的相關(guān)硬件程序?qū)崿F(xiàn),采用動(dòng)態(tài)重配置技術(shù)有效的提高了系統(tǒng)多模式交替工作情況下FPGA資源利用和功耗降低。本文的主要工作如下:首先,完成了一維線性陣列建模仿真,對(duì)互耦條件下的陣列天線進(jìn)行建模,闡述了互耦對(duì)方向圖的影響。給出了一種采用離線存儲(chǔ)HFSS仿真結(jié)果快速準(zhǔn)確逼近實(shí)際陣列天線方向圖的優(yōu)化計(jì)算方法,仿真分析了算法的高效性和有效性;接著,開展了改進(jìn)的降維四通道和差單脈沖角度估計(jì)方法研究。該算法對(duì)正方形柵格平面陣按行列降維進(jìn)行自適應(yīng)處理,并在降維之前進(jìn)行干擾方向的快速估計(jì)以選擇最佳降維維度。算法結(jié)合了主瓣保形的自適應(yīng)旁瓣干擾抑制,以及主瓣干擾自適應(yīng)和差對(duì)消,以形成主旁瓣干擾抑制的四通道波束,并用于單脈沖角度估計(jì)。算法引入了一種基于主瓣子空間的主瓣保形自適應(yīng)方法,該方法在進(jìn)行主瓣保形時(shí),無(wú)需獲取主瓣干擾的準(zhǔn)確方向。最后,針對(duì)某二維數(shù)字陣列雷達(dá)的實(shí)際要求,研制了一款同時(shí)對(duì)96通道中頻模擬信號(hào)進(jìn)行高速、同步采樣,采用V7系列FPGA和8核DSP進(jìn)行高性能信號(hào)處理的數(shù)字波束形成電路硬件平臺(tái)。針對(duì)電路設(shè)計(jì)中的電源、時(shí)鐘、配置、數(shù)據(jù)處理等電路的原理圖和PCB版圖進(jìn)行優(yōu)化設(shè)計(jì)。完成了電路電源調(diào)試測(cè)試、時(shí)鐘調(diào)試測(cè)試和模數(shù)轉(zhuǎn)換數(shù)據(jù)傳輸接口的調(diào)試測(cè)試。FPGA中數(shù)字下變頻、波束形成模塊的實(shí)測(cè)結(jié)果驗(yàn)證了相關(guān)程序設(shè)計(jì)的正確性。
[Abstract]:Fast target detection and tracking in complex electromagnetic environment has become one of the core technologies to be considered in the development and equipment of radar systems in the future. Digital array radar uses adaptive beamforming technology, which can effectively suppress strong interference in airspace. Aiming at the need of fast and accurate target angle estimation in digital array radar with sidelobe and main lobe interference, the array antenna modeling and four-channel fast adaptive monopulse algorithm are studied in this paper. Furthermore, according to the practical requirements of a two-dimensional digital array radar, a 96 channel if sampling digital beamforming circuit hardware platform is developed, and the hardware circuit debugging and testing is completed. According to the requirements of multi-mode operation of the system, the hardware program is implemented using four-channel adaptive monopulse technology. The dynamic reconfiguration technology can effectively improve the utilization of FPGA resources and reduce the power consumption under the condition of multi-mode alternation. The main work of this paper is as follows: firstly, the one-dimensional linear array modeling and simulation are completed, the array antenna under the condition of mutual coupling is modeled, and the influence of mutual coupling on the direction graph is discussed. In this paper, an optimization method for fast and accurate approximation of the actual array antenna pattern by off-line storage HFSS simulation results is presented, and the efficiency and effectiveness of the algorithm are analyzed. The improved dimensionality reduction four channel and differential monopulse angle estimation method are studied. The algorithm adaptively processes the dimensionality reduction of square raster plane array according to the row and column, and estimates the interference direction quickly before reducing the dimension to select the best dimension reduction degree. The main lobe conformal adaptive sidelobe interference suppression and the main lobe interference adaptive and differential cancellation are combined to form a four-channel beam for the main sidelobe interference suppression and it is used to estimate the angle of a single pulse. The algorithm introduces a principal lobe shape preserving adaptive method based on the principal lobe subspace. This method does not need to obtain the accurate direction of the main lobe interference when the main lobe is conserved. Finally, according to the practical requirements of a certain two-dimensional digital array radar, a high-speed and synchronous sampling of 96 channels if analog signals is developed at the same time. Digital beamforming circuit hardware platform using V7 series FPGA and 8 core DSP for high performance signal processing. The schematic diagram and PCB layout of power supply, clock, configuration, data processing and so on in circuit design are optimized. The circuit power supply debugging test, clock debugging test and analog to digital conversion data transmission interface debugging test. FPGA digital downconversion. The experimental results of beamforming module verify the correctness of the related program design.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN820

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