本文選題：同時(shí)同頻全雙工　切入點(diǎn)：FPGA　出處：《南京理工大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著移動(dòng)通信的快速發(fā)展,5G通信標(biāo)準(zhǔn)的制定工作逐步開展,作為5G關(guān)鍵技術(shù)之一的同時(shí)同頻全雙工技術(shù)受到國內(nèi)外的廣泛關(guān)注。本文以標(biāo)準(zhǔn)的LTE通信頻段為應(yīng)用背景,對(duì)同時(shí)同頻全雙工對(duì)消系統(tǒng)及其關(guān)鍵部件進(jìn)行了深入研究。相比在WARP、USDR等軟件無線電平臺(tái)上實(shí)現(xiàn)同時(shí)同頻全雙工系統(tǒng),本文的研究成果可以為實(shí)際應(yīng)用提供一體化、小型化的研究基礎(chǔ)。本文的主要研究?jī)?nèi)容如下:(1)設(shè)計(jì)了一種工作頻率為2.4GHz的同時(shí)同頻全雙工對(duì)消系統(tǒng)方案。此方案基于射頻重構(gòu)模擬自干擾對(duì)消技術(shù),先利用發(fā)射信號(hào)作參考本振信號(hào)與自干擾信號(hào)直接正交混頻,然后通過FPGA控制系統(tǒng)提取自干擾信號(hào)的相幅信息,進(jìn)而控制改進(jìn)型數(shù)字矢量調(diào)制器對(duì)發(fā)射參考信號(hào)進(jìn)行重構(gòu),最終實(shí)現(xiàn)對(duì)自干擾信號(hào)的對(duì)消。通過Matlab軟件仿真驗(yàn)證了該方案的可行性,取得較好的對(duì)消效果。(2)設(shè)計(jì)和實(shí)現(xiàn)了對(duì)消系統(tǒng)中的各模塊,包括自干擾對(duì)消模塊、自干擾信號(hào)檢測(cè)模塊和控制模塊。主要研制了正交耦合器、矢量調(diào)制器、合路器(功分器)、正交混頻器、射頻放大器、有源低通濾波器和誤差放大器以及FPGA控制電路等關(guān)鍵部件。(3)基于FPGA完成了 AD、DA和相幅計(jì)算等模塊構(gòu)成的整個(gè)系統(tǒng)軟件,并通過實(shí)測(cè)驗(yàn)證了本系統(tǒng)的可行性。
[Abstract]:With the rapid development of mobile communication, the establishment of 5G communication standard has been carried out step by step. As one of the key technologies of 5G, simultaneous full-duplex technology has attracted wide attention at home and abroad. In this paper, the standard LTE communication frequency band is used as the application background. In this paper, the simultaneous full duplex cancellation system and its key components are deeply studied. Compared with the software radio platform such as WARPU USDR, the research results of this paper can provide integration for practical applications. The main contents of this paper are as follows: (1) A scheme of simultaneous full-duplex cancellation with working frequency of 2.4 GHz is designed. This scheme is based on RF reconfigurable analog self-interference cancellation technology. First, the transmitted signal is used as the reference local oscillator signal and the self-interference signal is directly orthogonal mixed, then the phase amplitude information of the self-interference signal is extracted through the FPGA control system, and then the modified digital vector modulator is controlled to reconstruct the transmitted reference signal. Finally, the self-interference signal cancellation is realized. The feasibility of the scheme is verified by Matlab software simulation, and the design and implementation of each module in the cancellation system, including the self-interference cancellation module, is achieved. Self-interference signal detection module and control module. The orthogonal coupler, vector modulator, combiner (power divider, quadrature mixer, RF amplifier) are developed. Active low-pass filter, error amplifier and FPGA control circuit are the key components. The whole system software is completed based on FPGA, and the feasibility of the system is verified by actual measurement.
【學(xué)位授予單位】：南京理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN929.5

【參考文獻(xiàn)】

相關(guān)期刊論文 前4條

1 王俊;趙宏志;馬萬治;唐友喜;卿朝進(jìn);;同時(shí)同頻全雙工寬帶射頻自干擾抵消性能分析[J];通信學(xué)報(bào);2016年09期

2 焦秉立;馬猛;;同頻同時(shí)全雙工技術(shù)淺析[J];電信網(wǎng)技術(shù);2013年11期

3 張志亮;羅龍;邵士海;潘文生;沈瑩;唐友喜;;ADC量化對(duì)同頻全雙工數(shù)字自干擾消除的誤碼率性能分析[J];電子與信息學(xué)報(bào);2013年06期

4 萬德松;游彬;孫玲玲;;超高頻RFID高隔離度定向耦合器的設(shè)計(jì)[J];電子技術(shù)應(yīng)用;2008年11期

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本文編號(hào)：1626242