國密SM2在SoPC上快速運(yùn)算的研究和實(shí)現(xiàn)
發(fā)布時(shí)間:2018-02-10 11:59
本文關(guān)鍵詞: FPGA 橢圓曲線 SM2 SM3 SoC SoPC 出處:《揚(yáng)州大學(xué)》2017年碩士論文 論文類型:學(xué)位論文
【摘要】:國密SM2是國家密碼管理局頒布的一個(gè)基于橢圓曲線的公鑰密碼算法。SM2算法的實(shí)現(xiàn)速度取決于各部分算法的運(yùn)算速度,以往對SM2的研究也主要集中在算法的快速實(shí)現(xiàn)方面,包括雜湊算法、域元素的乘法及其他算法的快速實(shí)現(xiàn)上。針對國密算法在SoC上的快速實(shí)現(xiàn),本文選取SoPC作為實(shí)現(xiàn)的途徑,主要從SM2算法整體入手,分析考慮算法各部分的實(shí)現(xiàn),同時(shí)考慮硬件的資源的消耗以及軟硬件調(diào)用等問題。本文的主要工作有:(1)雜湊算法SM3實(shí)現(xiàn)方面:使用的是硬件實(shí)現(xiàn)方式,依據(jù)SoPC的內(nèi)部總線標(biāo)準(zhǔn)進(jìn)行接口封裝,設(shè)計(jì)和實(shí)現(xiàn)了可以提供給NiosⅡ嵌入式系統(tǒng)的直接使用的組件,在CycloneⅣ系列的EP4CE22F17C8N上進(jìn)行了實(shí)現(xiàn),測試表明,運(yùn)行頻率可以達(dá)165MHz,吞吐量為1184.8 Mbit/s;(2)域運(yùn)算方面:m的數(shù)值選為281位,使用高斯正規(guī)基進(jìn)行域運(yùn)算。在平方運(yùn)算上進(jìn)行了改進(jìn),一個(gè)周期內(nèi)實(shí)現(xiàn)多個(gè)移位運(yùn)算。對移位為281位的桶型移位器進(jìn)行了優(yōu)化,使用資源占用最少的混合編碼方式。高斯正規(guī)基上域元素的運(yùn)算均采用Avalon接口標(biāo)準(zhǔn)進(jìn)行封裝,可用于NiosⅡ嵌入式系統(tǒng)中;(3)整體實(shí)現(xiàn)方面:采用軟硬件結(jié)合的方式對算法進(jìn)行實(shí)現(xiàn),雜湊算法和域運(yùn)算采用硬件實(shí)現(xiàn),對于點(diǎn)乘運(yùn)算和大整數(shù)模逆等算法均采用軟件實(shí)現(xiàn),硬件系統(tǒng)資源需求約35000左右邏輯單元。
[Abstract]:Guomai SM2 is a public-key cryptosystem algorithm based on elliptic curve issued by the State Cryptography Administration. SM2 algorithm's implementation speed depends on the operation speed of each part of the algorithm. In the past, the research of SM2 mainly focused on the fast implementation of the algorithm. Including hash algorithm, multiplication of domain elements and fast implementation of other algorithms. In view of the fast implementation of the national secret algorithm on SoC, this paper selects SoPC as the way of implementation, mainly starts with the whole SM2 algorithm, and analyzes the implementation of each part of the algorithm. At the same time, the resource consumption of hardware and the transfer of hardware and software are considered. The main work of this paper is to implement the hash algorithm SM3: the hardware implementation is used, and the interface is encapsulated according to the internal bus standard of SoPC. This paper designs and implements a component that can be directly used in Nios 鈪,
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