用于特征提取的小尺寸事件型卷積處理器
發(fā)布時(shí)間：2018-11-20 21:39
【摘要】：設(shè)計(jì)了一款用于動(dòng)態(tài)視覺傳感器數(shù)據(jù)特征提取的小尺寸事件型卷積處理器,該卷積處理器包含了32×32的累加陣列、用于存儲(chǔ)卷積核的RAM陣列、左/右移位模塊、控制模塊和異步的事件讀出模塊。為了減小面積,設(shè)計(jì)了2 bit的32×32的RAM陣列來存儲(chǔ)所需的卷積核;在累加陣列中,采用7 bit的二進(jìn)制計(jì)數(shù)器代替?zhèn)鹘y(tǒng)的加法器來實(shí)現(xiàn)卷積核的累加操作,在0.18μm CMOS工藝下,每個(gè)卷積單元的面積為37.5μm×40μm,對(duì)于每個(gè)事件輸入輸出的最小延時(shí)為17 ns,能夠處理的最大事件率為12.5 Meps�；谠摼矸e處理器搭建了一個(gè)識(shí)別系統(tǒng),利用16個(gè)卷積處理器來提取特征,利用脈沖神經(jīng)網(wǎng)絡(luò)實(shí)現(xiàn)了分類識(shí)別。實(shí)驗(yàn)結(jié)果表明,使用2 bit卷積核的小尺寸卷積處理器能夠準(zhǔn)確完成對(duì)輸入事件的卷積操作,而且基于該卷積處理器所搭建的識(shí)別系統(tǒng)對(duì)MNIST數(shù)據(jù)庫(kù)的識(shí)別效率可以達(dá)到90.57%。
[Abstract]:A small event type convolution processor for feature extraction of dynamic visual sensor data is designed. The processor consists of 32 脳 32 accumulative arrays, RAM arrays for storing convolutional cores and left / right shift modules. Control module and asynchronous event readout module. In order to reduce the area, a 32 脳 32 RAM array of 2 bit is designed to store the required convolution cores. In the accumulative array, 7 bit binary counter is used instead of the traditional adder to realize the accumulative operation of the convolution kernel. In 0.18 渭 m CMOS process, the area of each convolution unit is 37.5 渭 m 脳 40 渭 m. Minimum delay of 17 ns, per event I / O maximum event rate of 12.5 Meps. Based on the convolution processor, a recognition system is built, 16 convolution processors are used to extract the features, and a pulse neural network is used to realize classification recognition. The experimental results show that the small size convolution processor using 2 bit convolution core can accurately complete the convolution operation of input events, and the recognition system based on this convolution processor can recognize the MNIST database with an efficiency of 90.57.
【作者單位】： 天津大學(xué)電子信息工程學(xué)院;
【分類號(hào)】：TN47
本文編號(hào)：2346117
[Abstract]:A small event type convolution processor for feature extraction of dynamic visual sensor data is designed. The processor consists of 32 脳 32 accumulative arrays, RAM arrays for storing convolutional cores and left / right shift modules. Control module and asynchronous event readout module. In order to reduce the area, a 32 脳 32 RAM array of 2 bit is designed to store the required convolution cores. In the accumulative array, 7 bit binary counter is used instead of the traditional adder to realize the accumulative operation of the convolution kernel. In 0.18 渭 m CMOS process, the area of each convolution unit is 37.5 渭 m 脳 40 渭 m. Minimum delay of 17 ns, per event I / O maximum event rate of 12.5 Meps. Based on the convolution processor, a recognition system is built, 16 convolution processors are used to extract the features, and a pulse neural network is used to realize classification recognition. The experimental results show that the small size convolution processor using 2 bit convolution core can accurately complete the convolution operation of input events, and the recognition system based on this convolution processor can recognize the MNIST database with an efficiency of 90.57.
【作者單位】： 天津大學(xué)電子信息工程學(xué)院;
【分類號(hào)】：TN47
【相似文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前3條
1 李大霞;cuda-convnet深層卷積神經(jīng)網(wǎng)絡(luò)算法的一種速度優(yōu)化[D];北京工業(yè)大學(xué);2015年
2 李倩玉;基于改進(jìn)深層網(wǎng)絡(luò)的視頻人臉識(shí)別研究[D];合肥工業(yè)大學(xué);2016年
3 劉玲;一種基于多卷積核特征提取的房顫?rùn)z測(cè)[D];河北大學(xué);2016年
，本文編號(hào)：2346117
本文鏈接：http://sikaile.net/kejilunwen/zidonghuakongzhilunwen/2346117.html
最近更新
教材專著
