【摘要】：陀螺儀傳感器是一種應用在慣性空間中的裝置,用于檢測角位移和相對角速度,在軍用領域和民用領域有著普遍地應用,已經(jīng)成為國內(nèi)外眾多科研機構(gòu)的研究熱點。在目前關(guān)于轉(zhuǎn)子式陀螺的研究中,還存在檢測精度不夠高,轉(zhuǎn)子轉(zhuǎn)速低,加工成本高等問題,因此哈爾濱工業(yè)大學MEMS中心提出了一種球碟轉(zhuǎn)子式微陀螺儀,該陀螺具有高精度、轉(zhuǎn)速高、低成本等明顯的優(yōu)勢。本文是基于球碟轉(zhuǎn)子式微陀螺設計了一款接口檢測ASIC電路。本文詳細地分析球碟轉(zhuǎn)子式陀螺微結(jié)構(gòu)及其工作原理,最終確定以相敏解調(diào)技術(shù)為核心的檢測電路方案,著重對整個接口檢測電路的進行系統(tǒng)設計與模塊劃分,詳細具體地完成各個電路單元的行為級設計,從而實現(xiàn)整體接口檢測ASIC電路的設計。在完成ASIC電路設計過程中,針對檢測電路的噪聲分析,重點實現(xiàn)C/V轉(zhuǎn)換電路單元和濾波放大單元的低噪聲設計,以及正弦載波信號電路單元的自動穩(wěn)幅控制設計,以確保ASIC電路達到降低輸出噪聲的要求。同時針對開關(guān)相敏解調(diào)信號的相位問題,通過0°~-180°移相電路單元的設計,實現(xiàn)解調(diào)方波信號相位誤差的調(diào)整,提升ASIC電路的線性度。本文綜合了整體電路的指標要求,在Cadence軟件平臺下完成了對檢測ASIC電路的整體以及各個單元模塊的行為級設計,驗證檢測電路的性能。從仿真結(jié)果分析得出,ASIC檢測電路的檢測范圍為5×10-2pF~5×10-8pF,電容相對分辨率為1×10-8,刻度因數(shù)為57.0938V/pF,非線性誤差為0.021%,等效輸出噪聲電壓為383.3nV/√Hz@40Hz。本文通過Cadence的Virtuoso工具進行版圖設計,在0.35μm的CMOS工藝下完成了整體ASIC的版圖設計,其版圖面積為3mm×2.85mm,并且完成了整體ASIC電路的后仿真驗證,結(jié)果滿足接口檢測電路的設計要求。
[Abstract]:Gyroscope sensor is a kind of device used in inertial space, which is used to detect angular displacement and relative angular velocity. Gyroscope sensor has been widely used in military and civil fields, and has become a hot research topic in many research institutions at home and abroad. In the current research on rotor gyroscope, there are still some problems, such as low measuring precision, low rotor speed and high machining cost. Therefore, the MEMS Center of Harbin University of Technology has put forward a kind of spherical disk rotor micro-gyroscope, which has high precision. High speed, low cost and other obvious advantages. In this paper, an interface detection ASIC circuit is designed based on the spherical disk rotor micro gyroscope. In this paper, the microstructure and working principle of the spherical disk rotor gyroscope are analyzed in detail, and the detection circuit scheme with phase sensitive demodulation technology as the core is determined. The system design and module partition of the whole interface detection circuit are emphasized. The behavior level design of each circuit unit is completed in detail, and the design of the whole interface detecting ASIC circuit is realized. In the process of ASIC circuit design, the low noise design of C / V conversion circuit unit and filter amplifier unit and the automatic amplitude stabilization control design of sinusoidal carrier signal circuit unit are mainly realized for the noise analysis of the detection circuit. To ensure that the ASIC circuit meets the requirements of reducing output noise. At the same time, aiming at the phase problem of switch phase sensitive demodulation signal, the phase error adjustment of demodulation square wave signal is realized through the design of 0 擄-180 擄phase shift circuit unit, and the linearity of ASIC circuit is improved. In this paper, the index requirements of the whole circuit are synthesized, and the design of the whole detection ASIC circuit and the behavior level of each unit module is completed under the Cadence software platform, and the performance of the detection circuit is verified. The results of simulation show that the detection range is 5 脳 10-2pF~5 脳 10 ~ (-8) PF, the relative resolution of capacitance is 1 脳 10 ~ (-8), the calibration factor is 57.0938 V / PF, the nonlinear error is 0.021, and the equivalent output noise voltage is 40 Hz / 383.3nV/. In this paper, the layout design of the whole ASIC is completed with the Virtuoso tool of Cadence, and the layout area of the whole ASIC is 3mm 脳 2.85mm in 0.35 渭 m CMOS process. The post-simulation verification of the whole ASIC circuit is completed, and the results meet the design requirements of the interface detection circuit.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN96;TP212

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本文編號：2144441