本文選題：深度學(xué)習(xí) + 神經(jīng)網(wǎng)絡(luò)�。� 參考：《哈爾濱工業(yè)大學(xué)》2017年碩士論文

【摘要】：近年來(lái),隨著人工智能的興起,以深度學(xué)習(xí)為代表的新型智能算法在機(jī)器視覺(jué)、圖像處理、模式識(shí)別等多個(gè)工程應(yīng)用領(lǐng)域得到成功應(yīng)用。但是,在工業(yè)大數(shù)據(jù)的沖擊下,傳統(tǒng)的軟件實(shí)現(xiàn)方式無(wú)法滿(mǎn)足實(shí)際工程低成本、高時(shí)效、高容錯(cuò)率的需求,因此急需尋求新的解決方案。現(xiàn)場(chǎng)可編程門(mén)陣列FPGA作為一種常用硬件開(kāi)發(fā)平臺(tái),擁有大規(guī)模的分布式硬件資源,并且具有開(kāi)發(fā)周期短、功耗低、性能好等特點(diǎn),非常適合計(jì)算密集型的深度學(xué)習(xí)算法的實(shí)現(xiàn)。本文以FPGA為硬件開(kāi)發(fā)平臺(tái),展開(kāi)深度學(xué)習(xí)的硬件化實(shí)現(xiàn)與優(yōu)化技術(shù)研究,主要研究?jī)?nèi)容如下:首先,深度學(xué)習(xí)硬件實(shí)現(xiàn)總體方案設(shè)計(jì)。詳細(xì)分析深度學(xué)習(xí)的理論基礎(chǔ)知識(shí),并以卷積神經(jīng)網(wǎng)絡(luò)為例,進(jìn)行網(wǎng)絡(luò)的拓?fù)浣Y(jié)構(gòu)和功能特點(diǎn)研究,給出本文硬件實(shí)現(xiàn)的具體網(wǎng)絡(luò)拓?fù)�。根�?jù)網(wǎng)絡(luò)拓?fù)涞慕Y(jié)構(gòu)特點(diǎn),進(jìn)行系統(tǒng)的總體方案設(shè)計(jì),將網(wǎng)絡(luò)拓?fù)溆成涞骄唧w的硬件電路。其次,完成算法硬件移植的優(yōu)化技術(shù)與架構(gòu)設(shè)計(jì)。選擇FPGA作為本文實(shí)現(xiàn)的硬件移植平臺(tái)。結(jié)合本文實(shí)現(xiàn)低功耗、高效率深度學(xué)習(xí)算法的目標(biāo),分別對(duì)硬件移植的優(yōu)化技術(shù)進(jìn)行深入研究,并應(yīng)用優(yōu)化技術(shù)完成對(duì)卷積神經(jīng)網(wǎng)絡(luò)從粗粒度到細(xì)粒度的并行架構(gòu)設(shè)計(jì)。然后,完成基于FPGA的卷積神經(jīng)網(wǎng)絡(luò)設(shè)計(jì)與實(shí)現(xiàn)。以FPGA為硬件開(kāi)發(fā)平臺(tái),完成卷積神經(jīng)網(wǎng)絡(luò)的整體架構(gòu)設(shè)計(jì)。根據(jù)卷積神經(jīng)網(wǎng)絡(luò)的結(jié)構(gòu)特點(diǎn),完成設(shè)計(jì)各功能電路模塊,包括卷積運(yùn)算模塊、抽樣運(yùn)算模塊、激活函數(shù)模塊。本文設(shè)計(jì)乒乓緩存結(jié)構(gòu),優(yōu)化數(shù)據(jù)傳輸結(jié)構(gòu)和數(shù)據(jù)緩存單元。用仿真軟件Modelsim分別驗(yàn)證各模塊功能正確性。最后,搭建系統(tǒng)整體實(shí)驗(yàn)平臺(tái)。依據(jù)現(xiàn)有的實(shí)驗(yàn)條件,配置網(wǎng)絡(luò)結(jié)構(gòu)與參數(shù),設(shè)計(jì)“FPGA+CPU”的異構(gòu)體系,完成卷積神經(jīng)網(wǎng)絡(luò)的硬件固化。以手寫(xiě)數(shù)字識(shí)別為具體應(yīng)用,完成軟件和硬件的對(duì)比實(shí)驗(yàn)。通過(guò)大量的實(shí)驗(yàn)統(tǒng)計(jì),結(jié)果表明本文設(shè)計(jì)的基于FPGA的卷積神經(jīng)網(wǎng)絡(luò)功能完整,性能優(yōu)異。
[Abstract]:In recent years, with the rise of artificial intelligence, a new intelligent algorithm, represented by deep learning, has been successfully applied in many engineering applications such as machine vision, image processing, pattern recognition and so on. However, under the impact of industrial big data, the traditional software implementation method can not meet the needs of low cost, high aging and high fault tolerance in practical projects, so it is urgent to find new solutions. Field Programmable Gate Array (FPGA), as a common hardware development platform, has large scale distributed hardware resources, short development cycle, low power consumption and good performance, so it is very suitable for the implementation of computationally intensive depth learning algorithm. In this paper, the hardware implementation and optimization technology of deep learning is studied on the platform of FPGA. The main contents are as follows: firstly, the overall scheme of hardware implementation of deep learning is designed. The basic theoretical knowledge of deep learning is analyzed in detail. Taking convolutional neural network as an example, the topological structure and functional characteristics of the network are studied, and the specific network topology realized by hardware in this paper is given. According to the structural characteristics of network topology, the overall scheme of the system is designed, and the network topology is mapped to the specific hardware circuit. Secondly, the optimization technology and architecture design of algorithm hardware transplantation are completed. FPGA is chosen as the hardware porting platform of this paper. Combined with the goal of realizing low power and high efficiency deep learning algorithm in this paper, the optimization technology of hardware transplantation is studied in depth, and the parallel architecture design of convolution neural network from coarse-grained to fine-grained is completed by using optimization technology. Then, the design and implementation of convolution neural network based on FPGA are completed. Using FPGA as hardware development platform, the overall architecture design of convolutional neural network is completed. According to the structural characteristics of the convolution neural network, the functional circuit modules are designed, including convolution operation module, sampling operation module and activation function module. This paper designs ping-pong cache structure, optimizes data transmission structure and data cache unit. The functional correctness of each module is verified by simulation software Modelsim. Finally, the whole experiment platform is built. According to the existing experimental conditions, configuration of network structure and parameters, design of "FPGA CPU" heterogeneous system, complete the hardware solidification of the convolutional neural network. Taking handwritten digit recognition as the concrete application, the contrast experiment between software and hardware is completed. Through a large number of experimental statistics, the results show that the convolution neural network based on FPGA has complete function and excellent performance.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TP18

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本文編號(hào)：1984816