超聲探測器多通道數據獲取系統的設計
發(fā)布時間:2018-12-15 03:42
【摘要】:超聲診斷是一項重要的醫(yī)學診斷技術,由于它具有無痛、無創(chuàng)、操作方便、顯示直觀、成本低廉等特點,在醫(yī)學診斷領域得到了廣泛的應用。就超聲診斷技術而言,超聲波的頻率越高,圖像分辨率就越高,顯示的結構也越精細。傳統的超聲探測器探測的超聲波頻率較低,導致圖像分辨率低,成像精度差,制約了超聲診斷技術的發(fā)展。因此,探索高分辨率超聲探測器成為近年來研究熱點。PVDF壓電膜具有壓電效應,當接收到超聲信號時會有感應電荷產生。本實驗室自主研發(fā)的Topmetal像素傳感器芯片具有體積小、位置分辨率高、響應速度快等優(yōu)勢,并且可以用來收集電荷,產生模擬電信號輸出。因此,利用PVDF壓電膜和Topmetal像素傳感器可以設計出滿足需求的高分辨率超聲探測器。本文的研究重點就是為此超聲探測器設計多通道數據獲取系統。該數據獲取系統通過8通道、12位高速模數轉換器對像素傳感器模擬輸出進行采樣,采樣率為25MSPS。ADC采樣的數據以LVDS形式傳送到FPGA后,經過差分到單端的轉換、延時調整、串并轉換、FIFO緩存后寫入128MByte的SDRAM中,然后通過PCIe總線將數據傳送到PC端保存并分析。PC端的控制指令通過PCIe總線傳送到FPGA中。本文的主要研究工作:1、硬件電路設計:包括芯片bonding板、芯片驅動板、ADC采樣板的硬件電路設計。bonding板實現芯片pad的引出。驅動板提供芯片控制信號、外部復位電平和模擬輸出驅動。ADC采樣板用來對像素傳感器的模擬輸出進行采樣。2、系統邏輯設計:包括時鐘管理模塊、ADC寄存器配置模塊、差分轉換模塊、延時控制模塊、串并轉換模塊、數據緩存模塊以及QSYS系統設計。3、系統軟件設計:利用Linux操作系統下PCIe驅動用戶接口函數實現了ADC寄存器設置、數據延時設置、延時分析和傳輸誤碼分析等功能。4、系統測試:包括硬件電子學各模塊測試和整個超聲探測系統的測試。測試結果表明,數據獲取系統可穩(wěn)定工作在25MSPS采樣率下。
[Abstract]:Ultrasonic diagnosis is an important medical diagnosis technology. Because of its painless, non-invasive, convenient operation, visual display, low cost and so on, it has been widely used in the field of medical diagnosis. As far as ultrasonic diagnosis technology is concerned, the higher the ultrasonic frequency, the higher the image resolution and the finer the display structure. The low ultrasonic frequency detected by traditional ultrasonic detectors leads to low image resolution and poor imaging accuracy, which restricts the development of ultrasonic diagnosis technology. Therefore, the exploration of high resolution ultrasonic detectors has become a hot topic in recent years. PVDF piezoelectric film has piezoelectric effect and inductive charge will be generated when the ultrasonic signal is received. The Topmetal pixel sensor chip developed by our laboratory has the advantages of small size, high position resolution, fast response speed, and can be used to collect charge and generate analog electrical signal output. Therefore, high resolution ultrasonic detector can be designed by using PVDF piezoelectric film and Topmetal pixel sensor. The key point of this paper is to design a multi-channel data acquisition system for ultrasonic detector. The data acquisition system samples the analog output of pixel sensor through 8 channels and 12 bits high speed A / D converter. After the data sampled by 25MSPS.ADC is transmitted to FPGA in the form of LVDS, after the difference to single terminal conversion, the delay is adjusted. Series-parallel conversion, FIFO cache, then write to 128MByte SDRAM, and then transfer data to PC through PCIe bus to save and analyze. PC control instructions are sent to FPGA via PCIe bus. The main research work of this paper is as follows: 1. Hardware circuit design: including the hardware circuit design of chip bonding board, chip driver board and ADC sampling board. Bonding board realizes the extraction of chip pad. The driver board provides chip control signal, external reset level and analog output driver. ADC sampling board is used to sample the analog output of pixel sensor. 2. System logic design: including clock management module, ADC register configuration module, Differential conversion module, delay control module, series-parallel conversion module, data cache module and QSYS system design. 3. System software design: using PCIe driver user interface function under Linux operating system to realize ADC register setting. Data delay setting, delay analysis, transmission error analysis and other functions. 4, system testing: including hardware and electronics modules test and the whole ultrasonic detection system testing. The test results show that the data acquisition system can work stably under the 25MSPS sampling rate.
【學位授予單位】:華中師范大學
【學位級別】:碩士
【學位授予年份】:2015
【分類號】:TH776
本文編號:2379902
[Abstract]:Ultrasonic diagnosis is an important medical diagnosis technology. Because of its painless, non-invasive, convenient operation, visual display, low cost and so on, it has been widely used in the field of medical diagnosis. As far as ultrasonic diagnosis technology is concerned, the higher the ultrasonic frequency, the higher the image resolution and the finer the display structure. The low ultrasonic frequency detected by traditional ultrasonic detectors leads to low image resolution and poor imaging accuracy, which restricts the development of ultrasonic diagnosis technology. Therefore, the exploration of high resolution ultrasonic detectors has become a hot topic in recent years. PVDF piezoelectric film has piezoelectric effect and inductive charge will be generated when the ultrasonic signal is received. The Topmetal pixel sensor chip developed by our laboratory has the advantages of small size, high position resolution, fast response speed, and can be used to collect charge and generate analog electrical signal output. Therefore, high resolution ultrasonic detector can be designed by using PVDF piezoelectric film and Topmetal pixel sensor. The key point of this paper is to design a multi-channel data acquisition system for ultrasonic detector. The data acquisition system samples the analog output of pixel sensor through 8 channels and 12 bits high speed A / D converter. After the data sampled by 25MSPS.ADC is transmitted to FPGA in the form of LVDS, after the difference to single terminal conversion, the delay is adjusted. Series-parallel conversion, FIFO cache, then write to 128MByte SDRAM, and then transfer data to PC through PCIe bus to save and analyze. PC control instructions are sent to FPGA via PCIe bus. The main research work of this paper is as follows: 1. Hardware circuit design: including the hardware circuit design of chip bonding board, chip driver board and ADC sampling board. Bonding board realizes the extraction of chip pad. The driver board provides chip control signal, external reset level and analog output driver. ADC sampling board is used to sample the analog output of pixel sensor. 2. System logic design: including clock management module, ADC register configuration module, Differential conversion module, delay control module, series-parallel conversion module, data cache module and QSYS system design. 3. System software design: using PCIe driver user interface function under Linux operating system to realize ADC register setting. Data delay setting, delay analysis, transmission error analysis and other functions. 4, system testing: including hardware and electronics modules test and the whole ultrasonic detection system testing. The test results show that the data acquisition system can work stably under the 25MSPS sampling rate.
【學位授予單位】:華中師范大學
【學位級別】:碩士
【學位授予年份】:2015
【分類號】:TH776
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1 劉軍;超聲探測器多通道數據獲取系統的設計[D];華中師范大學;2015年
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