傳統(tǒng)大體型衛(wèi)星的研發(fā)(Research and Development,R&D)往往需要成千上百個(gè)團(tuán)隊(duì)協(xié)同工作。開發(fā)周期通常很長而且成本也很高。小衛(wèi)星的發(fā)展已成為一個(gè)熱門的研究話題。世界各地許多國家和組織正在探索在近地軌道(Lower Earth Orbit,LEO)上的星群中部署一顆中型母衛(wèi)星和數(shù)百個(gè)筆記本電腦大小的衛(wèi)星,旨在開發(fā)更多應(yīng)用,如情報(bào)偵查、戰(zhàn)時(shí)通信恢復(fù)、合成孔徑雷達(dá)等。在單一平臺上只采用單一的編程語言和單一的開發(fā)工具的傳統(tǒng)設(shè)計(jì)方法不能很好地滿足大規(guī)模生產(chǎn)和短開發(fā)周期的要求。與可充電設(shè)備中的通信相比,小衛(wèi)星通信系統(tǒng)在尺寸,重量和功率(Size,Weight,and Power,SWaP)以及硬件資源方面有更為苛刻的限制。此外,小衛(wèi)星數(shù)量的急劇增加,較小的星間間距使得衛(wèi)星的可用頻譜更加擁擠。因此,解決這些問題就需要:(1)一種新的設(shè)計(jì)方法用來提高設(shè)計(jì)效率并能快速進(jìn)行原型機(jī)驗(yàn)證,一個(gè)具有并行發(fā)收、動態(tài)調(diào)整速率和信號帶寬并支持多種射頻(Radio Frequency,RF)協(xié)議標(biāo)準(zhǔn)能力的平臺。(2)改進(jìn)的和優(yōu)化的算法、簡化的結(jié)構(gòu)以及新的方案用來降低計(jì)算復(fù)雜度、硬件資源使用...

【文章頁數(shù)】：193 頁

【學(xué)位級別】：博士

【文章目錄】：
ABSTRACT
摘要
List of Symbols
List of Abbreviations
Chapter 1 Introduction
    1.1 Background
    1.2 Research Motivations
    1.3 Related Works
        1.3.1 Research Topics on Small Satellites
        1.3.2 Applications of MBD Approach
        1.3.3 SDR Implementations
        1.3.4 FPGA Implementations
        1.3.5 Research on MARC
    1.4 Research Objectives
    1.5 Main Contributions
    1.6 Organization
Chapter 2 Model-Based Design Approach for SDRs in ISCs
    2.1 Preliminary
    2.2 Features of SDRs in ISCs
        2.2.1 Power Supply
        2.2.2 Frequency Allocation
        2.2.3 Coding Schemes and Rate
        2.2.4 Modulation Types
    2.3 Superiorities of MBD for SDRs
    2.4 Model-Based Design Flow for SDRs
        2.4.1 ISC SDR Model
        2.4.2 Automatic Code Generation
        2.4.3 Deployment of Customized IP Cores
        2.4.4 Simulation
        2.4.5 In-the-loop Testing and Verification
    2.5 SDR Challenges in Small Satellites Application
        2.5.1 Space Environment Challenges
        2.5.2 Software Challenges
        2.5.3 Hardware Challenges
    2.6 Summary
Chapter 3 Low Power SDR Design for Transmitter Prototype
    3.1 Overview of SDR Platform and Transmitter Prototype
        3.1.1 Inner Architecture of ADC/DAC
        3.1.2 Inner Architecture of FPGA
        3.1.3 SDR Structure of Transmitter Prototype
    3.2 MBD for Transmitter Baseband Processor
        3.2.1 LDPC Encoder
        3.2.2 OQPSK Modulator
        3.2.3 Pulse Shaping Filter
    3.3 Transmitter RF Front End
    3.4 Summary
Chapter 4 Low Power SDR Design for Receiver Prototype
    4.1 SDR Structure of Receiver Prototype
    4.2 MBD for Receiver Baseband Processor
        4.2.1 Automatic Gain Control
        4.2.2 Frequency Compensation
        4.2.3 Timing Recovery
        4.2.4 Frame Synchronization
        4.2.5 Soft-Output Demodulator
        4.2.6 LDPC Decoder
    4.3 Receiver RF Front End
    4.4 Summary
Chapter 5 Low Power Scheme and SDR Design for Small Satellites Cluster
    5.1 Typical Structures of Small Satellites Cluster
    5.2 Inter-Satellite Link Equation
    5.3 Relay Model and SDR Design for Small Satellites Cluster
        5.3.1 System Model and its Capacity Region
        5.3.2 Application of a Joint Network LDPC Code over MARC
        5.3.3 Joint Network LDPC Decoding
        5.3.4 SDR Design for the Relay Satellite
        5.3.5 SDR Design for the Mother Satellite
    5.4 Simulation Results
    5.5 Summary
Chapter 6 FPGA Implementation and Performance Analysis
    6.1 Interfaces Between the Host Computer and SDR Platform
        6.1.1 Bit Data Generation Module
        6.1.2 Data Packing and Unpacking Module
        6.1.3 Data Printing Module
        6.1.4 Transmitter and Receiver Configuration
    6.2 Real-Time Test
        6.2.1 Test Platform
        6.2.2 Signals Collection and Analysis
        6.2.3 Real-time Data Printing
        6.2.4 Signal Quality in Real-Time Transmission
    6.3 Hardware Utilization and Power Consumption
    6.4 Performance Analysis and Comparison
    6.5 Summary
Chapter 7 Conclusion
    7.1 Research Conclusion
    7.2 Limitations of Current Work
    7.3 Future Works
References
Acknowledgements
Resume



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