【摘要】：隨著視頻技術(shù)的發(fā)展,視頻的分辨率變得越來越高。目前,高清、超高清視頻已經(jīng)成為主流,相應每一幀視頻信息量也急劇增加,對超高清視頻的存儲和傳輸帶來極大挑戰(zhàn)。視頻編碼技術(shù)可以為視頻的壓縮和傳輸提供了很好的解決方案。最新的視頻編碼標準HEVC/H.265(High Efficiency Video Coding),為高清和超高清視頻提供了良好的壓縮效率。在相同視頻清晰度的情況下,HEVC比上一代視頻編碼標準H.264減少了近50%的編碼比特率。在提高壓縮率的同時,HEVC編碼復雜度和編碼時間也相應的增加,對視頻編解碼的實時性非常不利。因此,為了實現(xiàn)超高清視頻的實時傳輸,需要設計高吞吐和高性能的HEVC編解碼芯片。本文主要圍繞HEVC編碼器中幀間預測,提出了一種高吞吐的整像素運動估計和分像素運動估計的硬件架構(gòu)。具體工作如下:(1)運動估計是HEVC幀間預測中最核心的模塊,為了提高視頻圖像的壓縮效率,其預測單元(PU)的尺寸和數(shù)量都急劇增加,造成運動估計的高復雜度,為高清和超高清視頻的實時處理帶來巨大挑戰(zhàn)。本文針對整像素運動估計,提出了一種適合硬件實現(xiàn)的運動估計算法,并設計了硬件架構(gòu)。該算法分為粗搜索和細搜索兩個階段,對同一深度的預測單元共享了其粗搜索結(jié)果,增大了細搜索階段PU的并行度。對硬件設計部分,在粗搜索階段,設計了一種層次復用的參考像素調(diào)度策略,并為其組織了流水線結(jié)構(gòu),保證了參考像素的完全復用和實現(xiàn)了搜索點之間有規(guī)律的流水線匹配代價計算;在細搜索階段,采用光柵掃描式搜索策略,復用了粗搜索時的參考像素寄存器和SAD計算單元,大大減少了硬件資源。在90nm的工藝下,綜合結(jié)果表明最高頻率可以達到377MHz,在搜索范圍為±64時,能夠達到超高清視頻圖像3840×2160@60fps的實時處理速度。(2)本文針對運動估計中分像素運動模塊進行了硬件設計,對插值計算單元設計了共享半像素和1/4像素濾波器的插值濾波單元,并在不同插值位置間共享插值結(jié)果,減少了插值個數(shù)。通過分析搜索點的數(shù)據(jù)的處理順序,不同搜索階段,設計了插值和匹配代價計算單元流水線結(jié)構(gòu),并優(yōu)化了插值濾波單元電路結(jié)構(gòu)。最后可達到3840×2160@30fps的處理速度。
[Abstract]:With the development of video technology, the resolution of video becomes higher and higher. At present, HD, UHD video has become the mainstream, the corresponding video information per frame has increased dramatically, which brings great challenges to the storage and transmission of UHD video. Video coding technology can provide a good solution for video compression and transmission. The latest video coding standard HEVC/H.265 (High Efficiency Video Coding), provides high-definition and high-definition video compression efficiency. With the same video definition, HEVC reduces the coding bit rate by nearly 50% compared with the previous video coding standard H. 264. At the same time, the complexity and time of HEVC coding are also increased, which is not good for the real-time performance of video coding and decoding. Therefore, in order to realize the real-time transmission of ultra high-definition video, we need to design high throughput and high performance HEVC codec chip. This paper mainly focuses on inter-frame prediction in HEVC encoder, and proposes a hardware architecture of integrated pixel motion estimation and sub-pixel motion estimation with high throughput. The main works are as follows: (1) Motion estimation is the most important module in HEVC inter-frame prediction. In order to improve the compression efficiency of video image, the size and number of (PU) of the prediction unit increase dramatically, resulting in the high complexity of motion estimation. It brings great challenges for real-time processing of HD and UHD video. In this paper, a motion estimation algorithm suitable for hardware implementation is proposed and the hardware architecture is designed for integer pixel motion estimation. The algorithm is divided into coarse search and fine search. The rough search results are shared for the prediction units of the same depth, and the parallelism of PU in the fine search phase is increased. For hardware design part, in rough search phase, a hierarchical multiplexing reference pixel scheduling strategy is designed, and pipeline structure is organized for it. It ensures the complete reuse of reference pixels and realizes the regular pipeline matching cost calculation between search points. In the fine search phase, the raster scan search strategy is used to reuse the reference pixel registers and SAD computing units in rough search, which greatly reduces the hardware resources. Under the 90nm process, the synthetic results show that the maximum frequency can reach 377MHz, and when the search range is 鹵64, The real-time processing speed of ultra high definition video image is 3840 脳 2160@60fps. (2) the hardware design of sub-pixel motion module in motion estimation is presented in this paper. The interpolation filter unit with shared half pixel and 1 / 4 pixel filter is designed for the interpolation computing unit, and the interpolation results are shared among different interpolation positions, thus reducing the number of interpolation. By analyzing the data processing order of search points, the pipeline structure of interpolation and matching cost computing unit is designed in different search stages, and the circuit structure of interpolation filter unit is optimized. Finally, the processing speed of 3840 脳 2160@30fps can be achieved.
【學位授予單位】：中國科學技術(shù)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN919.81

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