基于H.265編碼的視頻處理系統(tǒng)設(shè)計(jì)
發(fā)布時(shí)間：2018-11-13 08:56
【摘要】：隨著視頻技術(shù)在各個(gè)領(lǐng)域的深入應(yīng)用,視頻也向著更高的分辨率、更高的幀頻、更高壓縮率的方向發(fā)展。如果依舊采用H.264/AVC(Advanced Video Coding)的編碼方式,由于其固定的宏塊劃分、基于上下文的熵編碼和去塊濾波的串行處理方式,使得在編碼高清、超高清視頻質(zhì)量和編碼效率上顯得不足。新一代編碼技術(shù)H.265/HEVC(High Efficiency Video Coding)應(yīng)運(yùn)而生。H.265/HEVC采用更大宏塊、更為靈活的劃塊機(jī)制、更為精確的預(yù)測(cè)等一系列技術(shù)有效的提高了編碼壓縮性能。但是其復(fù)雜度是H.264/AVC的5倍至10倍,這意味著在壓縮相同圖像下,H.265/HEVC需要較H.264/AVC幾倍的數(shù)據(jù)處理能力。這樣就對(duì)處理器的處理性能及功耗等提出了挑戰(zhàn)。同時(shí)帶來的好處是:在提供同樣的視頻質(zhì)量下,H.265/HEVC可以將數(shù)據(jù)帶寬減少50%。這使得在不改變現(xiàn)有網(wǎng)絡(luò)帶寬的條件下傳輸更高分辨率和幀速率的高清和超高清視頻成為了一種可能。本文是基于H.265/HEVC編碼對(duì)高清、超高清視頻進(jìn)行處理。根據(jù)H.265/HEVC編碼的復(fù)雜度,設(shè)計(jì)了一套基于DSP、高性能FPGA、大容量數(shù)據(jù)緩存模塊和PCIe高速串行總線等的高帶寬H.265/HEVC壓縮編碼的視頻處理系統(tǒng)。該視頻處理系統(tǒng)的核心編碼器件是TI公司生產(chǎn)的TMS320C6678高性能DSP器件。其具有8個(gè)內(nèi)核,主要實(shí)現(xiàn)H.265/HEVC編碼算法。該視頻處理系統(tǒng)的核心主控制器件是Xlinx公司生產(chǎn)的XC7K410T FPGA器件。完成編碼處理器TMS320C6678與PC之間高速數(shù)據(jù)交換以及大容量和高帶寬的原始視頻序列和編碼后數(shù)據(jù)流的緩沖。高速數(shù)據(jù)交換模塊主要用于對(duì)原始視頻序列的高速傳輸,采用高速串行接口現(xiàn)實(shí),FPGA與PC之間的高速串行接口采用PCIe協(xié)議,其為新一代高速串行總線,具有傳輸速率快,傳輸穩(wěn)定、可靠的特點(diǎn);FPGA與DSP編碼器之間高速串行接口采用SRIO協(xié)議,此協(xié)議是嵌入系統(tǒng)中芯片間、板級(jí)間高性能、低時(shí)延、少引腳、可靠的基于包交換的高速串行互連技術(shù)。視頻緩存模塊主要用于存取視頻原始序列和壓縮后的H.265碼流,采用多塊DDR3L顆粒并聯(lián)實(shí)現(xiàn)緩存,DDR3L具有高帶寬、大容量、低功耗的特點(diǎn)。最后,通過對(duì)本系統(tǒng)的各個(gè)接口模塊進(jìn)行仿真和調(diào)試,驗(yàn)證了該視頻處理系統(tǒng)設(shè)計(jì)的物理邏輯可行性。利用TMS320C6678處理器實(shí)現(xiàn)了對(duì)YUV 4:2:0視頻原始序列的H.265/HEVC標(biāo)準(zhǔn)編碼。并通過PC端軟件初步分析了H.265/HEVC壓縮后的碼流。實(shí)現(xiàn)表明該系統(tǒng):基于H.265編碼的由高性能DSP和高性能FPGA組成架構(gòu)視頻處理系統(tǒng)對(duì)于高清、超高清視頻的壓縮、傳輸、存儲(chǔ)等是可行的。同時(shí)具有一定的研究?jī)r(jià)值和應(yīng)用前景。
[Abstract]:With the further application of video technology in various fields, video is developing towards higher resolution, higher frame rate and higher compression ratio. If H.264/AVC (Advanced Video Coding) coding method is still adopted, because of its fixed macroblock partition, context-based entropy coding and de-blocking filtering serial processing, it makes high-definition coding. UHD video quality and coding efficiency is insufficient. A new generation of coding technology, H.265/HEVC (High Efficiency Video Coding), emerges as the times require. A series of techniques, such as larger macroblock, more flexible block mechanism and more accurate prediction, are used in H.265/HEVC to effectively improve the performance of coding compression. But its complexity is 5 to 10 times that of H.264/AVC, which means that H.265/HEVC needs several times as much data processing power as H.264/AVC in the same image compression. In this way, the processing performance and power consumption of the processor are challenged. At the same time, the benefits are that H.265/HEVC can reduce data bandwidth by 50% with the same video quality. This makes it possible to transmit high-definition and ultra-high-definition video with higher resolution and frame rate without changing the current network bandwidth. This paper is based on H.265/HEVC coding for high-definition, ultra-high-definition video processing. According to the complexity of H.265/HEVC coding, a high bandwidth H.265/HEVC compression coding system based on DSP, high performance FPGA, large capacity data buffer module and PCIe high speed serial bus is designed. The core encoder of this video processing system is TMS320C6678 high performance DSP device produced by TI Company. It has 8 kernels and mainly implements H.265/HEVC coding algorithm. The core controller of the video processing system is the XC7K410T FPGA device produced by Xlinx Company. High speed data exchange between TMS320C6678 and PC as well as buffering of raw video sequences and encoded data streams with large capacity and high bandwidth are completed. The high-speed data exchange module is mainly used for the high-speed transmission of the original video sequence. The high-speed serial interface between FPGA and PC is based on the PCIe protocol, which is a new generation of high-speed serial bus with high transmission rate. Stable and reliable transmission; The high speed serial interface between FPGA and DSP encoder adopts SRIO protocol, which is a high speed serial interconnection technology based on packet switching. The video buffer module is mainly used to access the original video sequence and compressed H.265 bitstream. The DDR3L has the characteristics of high bandwidth, large capacity and low power consumption. Finally, the physical logic feasibility of the design of the video processing system is verified by the simulation and debugging of each interface module of the system. The H.265/HEVC standard encoding of YUV 4:2:0 video sequence is realized by using TMS320C6678 processor. The code stream after H.265/HEVC compression is analyzed by PC software. The implementation shows that the video processing system based on H.265 encoding is feasible for the compression, transmission and storage of high-definition, ultra-high-definition video, which is composed of high performance DSP and high performance FPGA. At the same time, it has certain research value and application prospect.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN919.81
本文編號(hào)：2328621
[Abstract]:With the further application of video technology in various fields, video is developing towards higher resolution, higher frame rate and higher compression ratio. If H.264/AVC (Advanced Video Coding) coding method is still adopted, because of its fixed macroblock partition, context-based entropy coding and de-blocking filtering serial processing, it makes high-definition coding. UHD video quality and coding efficiency is insufficient. A new generation of coding technology, H.265/HEVC (High Efficiency Video Coding), emerges as the times require. A series of techniques, such as larger macroblock, more flexible block mechanism and more accurate prediction, are used in H.265/HEVC to effectively improve the performance of coding compression. But its complexity is 5 to 10 times that of H.264/AVC, which means that H.265/HEVC needs several times as much data processing power as H.264/AVC in the same image compression. In this way, the processing performance and power consumption of the processor are challenged. At the same time, the benefits are that H.265/HEVC can reduce data bandwidth by 50% with the same video quality. This makes it possible to transmit high-definition and ultra-high-definition video with higher resolution and frame rate without changing the current network bandwidth. This paper is based on H.265/HEVC coding for high-definition, ultra-high-definition video processing. According to the complexity of H.265/HEVC coding, a high bandwidth H.265/HEVC compression coding system based on DSP, high performance FPGA, large capacity data buffer module and PCIe high speed serial bus is designed. The core encoder of this video processing system is TMS320C6678 high performance DSP device produced by TI Company. It has 8 kernels and mainly implements H.265/HEVC coding algorithm. The core controller of the video processing system is the XC7K410T FPGA device produced by Xlinx Company. High speed data exchange between TMS320C6678 and PC as well as buffering of raw video sequences and encoded data streams with large capacity and high bandwidth are completed. The high-speed data exchange module is mainly used for the high-speed transmission of the original video sequence. The high-speed serial interface between FPGA and PC is based on the PCIe protocol, which is a new generation of high-speed serial bus with high transmission rate. Stable and reliable transmission; The high speed serial interface between FPGA and DSP encoder adopts SRIO protocol, which is a high speed serial interconnection technology based on packet switching. The video buffer module is mainly used to access the original video sequence and compressed H.265 bitstream. The DDR3L has the characteristics of high bandwidth, large capacity and low power consumption. Finally, the physical logic feasibility of the design of the video processing system is verified by the simulation and debugging of each interface module of the system. The H.265/HEVC standard encoding of YUV 4:2:0 video sequence is realized by using TMS320C6678 processor. The code stream after H.265/HEVC compression is analyzed by PC software. The implementation shows that the video processing system based on H.265 encoding is feasible for the compression, transmission and storage of high-definition, ultra-high-definition video, which is composed of high performance DSP and high performance FPGA. At the same time, it has certain research value and application prospect.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN919.81
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