【摘要】：針對(duì)目前存儲(chǔ)測(cè)試系統(tǒng)中存有的數(shù)據(jù)傳輸慢,經(jīng)常出現(xiàn)錯(cuò)誤的顯著問題,設(shè)計(jì)基于USB 3.0接口的高速數(shù)據(jù)傳輸系統(tǒng)。該設(shè)計(jì)以FPGA作為主控芯片,采用負(fù)延遲與乒乓緩存的方式將A/D轉(zhuǎn)換的數(shù)據(jù)高速緩存到DDR2 SDRAM中。設(shè)計(jì)了GPIFⅡ通用可編程接口和手動(dòng)DMA通道,實(shí)現(xiàn)了USB 3.0同步從FIFO模式的高速數(shù)據(jù)傳輸。系統(tǒng)分析測(cè)試和實(shí)驗(yàn)結(jié)果表明,該系統(tǒng)實(shí)現(xiàn)了數(shù)據(jù)的高速可靠傳輸,能有效解決大容量數(shù)據(jù)采集后的數(shù)據(jù)高速傳輸問題。
[Abstract]:A high-speed data transmission system based on USB 3.0 interface is designed in view of the obvious problems of slow data transmission and frequent errors in the current storage and testing system. In this design, FPGA is used as the main control chip, and negative delay and ping-pong buffers are used to cache the A- / D converted data into the DDR2 SDRAM. The GPIF 鈪，

本文編號(hào)：2295017