發(fā)布時(shí)間：2018-09-03 12:30

【摘要】：隨著軟件無線電技術(shù)的快速發(fā)展,接收機(jī)技術(shù)在國內(nèi)外領(lǐng)域已十分成熟,然而寬帶可重構(gòu)數(shù)字射頻發(fā)射機(jī)的研究卻比較少。寬帶可重構(gòu)數(shù)字射頻發(fā)射機(jī)直接采用數(shù)字化的混頻器和頻率合成器,簡(jiǎn)化了使用模擬器件所帶來的電路設(shè)計(jì)和調(diào)試的復(fù)雜度,使無線通信系統(tǒng)性能變得更加穩(wěn)定。本文首先提出一種寬帶可重構(gòu)數(shù)字射頻發(fā)射機(jī)實(shí)現(xiàn)的整體方案,并主要分析了該發(fā)射機(jī)中基于FPGA實(shí)現(xiàn)的數(shù)字信號(hào)合成的具體方案,該數(shù)字信號(hào)合成主要包括數(shù)字上變頻與特定頻率的信號(hào)合成,并對(duì)其涉及到的關(guān)鍵技術(shù)如低通增量求和調(diào)制、極坐標(biāo)轉(zhuǎn)換、DDS數(shù)字調(diào)相技術(shù)進(jìn)行了詳細(xì)的分析。本文學(xué)習(xí)研究的主要成果如下:1)對(duì)涉及到的低通增量求和調(diào)制技術(shù)進(jìn)行研究設(shè)計(jì),該調(diào)制技術(shù)具有降噪抗干擾能力�；贛ATLAB分別對(duì)一階、二階增量求和調(diào)制器進(jìn)行SIMULINK建模,過采樣率OSR均設(shè)為128,1 bit量化,最后通過仿真分析得出二階調(diào)制器的信噪比約為99 d B,而一階的約為73 d B,均與直接用信噪比公式計(jì)算出的值相近,同時(shí)對(duì)比二者最終輸出信號(hào)的頻譜圖得出二階調(diào)制器的降噪效果明顯優(yōu)于一階,信噪比也明顯提高了約26 dB的結(jié)論。2)對(duì)涉及到的極坐標(biāo)轉(zhuǎn)換技術(shù)進(jìn)行研究設(shè)計(jì),實(shí)現(xiàn)已調(diào)I、Q信號(hào)的極坐標(biāo)轉(zhuǎn)換。首先設(shè)定I、Q信號(hào)分別為頻率5 Hz的余弦與正弦波,然后用MATLAB編程仿真得出極坐標(biāo)轉(zhuǎn)換后的極徑r為一個(gè)常數(shù),極角q為周期性變化鋸齒波的結(jié)論。3)對(duì)涉及到的DDS數(shù)字調(diào)相技術(shù)進(jìn)行研究設(shè)計(jì),用來合成所需頻率并具有相位調(diào)制的信號(hào)。首先建立SIMULINK模型,設(shè)置參考源cf為125 MHz,相位累加器位數(shù)N為20,分別讓頻率控制字K取2~15、2~13、2~11進(jìn)行仿真,得到對(duì)應(yīng)信號(hào)的頻譜圖,由頻譜圖得到信號(hào)頻率分別約為2.45*10~7 rad/s,6.14*10~6rad/s,1.53*10~6 rad/s,結(jié)果滿足該系統(tǒng)合成信號(hào)頻f_0=K·f_c/2~N的計(jì)算公式,也進(jìn)一步說明變化K就能調(diào)節(jié)DDS系統(tǒng)最終合成信號(hào)的頻率值;其次,對(duì)實(shí)現(xiàn)普通的2PSK調(diào)制技術(shù)的鍵控法與模擬法進(jìn)行SIMULINK建模仿真,為DDS數(shù)字調(diào)相技術(shù)的仿真驗(yàn)證奠定基礎(chǔ);最后,對(duì)DDS數(shù)字調(diào)相技術(shù)建立SIMULINK模型,各參數(shù)設(shè)置與之前的DDS系統(tǒng)相同,僅以K取182為例進(jìn)行仿真,通過設(shè)置固定周期的偏轉(zhuǎn)相位信號(hào),最后輸出2PSK信號(hào),從而驗(yàn)證DDS系統(tǒng)具有數(shù)字調(diào)相功能。4)對(duì)該發(fā)射機(jī)中數(shù)字上變頻與信號(hào)合成的整個(gè)方案在FPGA中實(shí)現(xiàn),最終下載至FPGA開發(fā)芯片上,并調(diào)用CHIPSCOPE軟件觀察各個(gè)關(guān)鍵模塊輸出信號(hào)波形,計(jì)算得出輸出信號(hào)的頻率約為21.4 MHz,這與起初設(shè)置的頻率控制字K取764504178對(duì)應(yīng)的頻率是相近的,從而驗(yàn)證整個(gè)方案的合理性。
[Abstract]:With the rapid development of software radio technology, receiver technology has been very mature at home and abroad, but the research of broadband reconfigurable digital RF transmitter is less. Digital mixer and frequency synthesizer are used directly in broadband reconfigurable digital radio frequency transmitter, which simplifies the complexity of circuit design and debugging brought by using analog devices, and makes the performance of wireless communication system more stable. In this paper, a whole scheme of broadband reconfigurable digital radio frequency transmitter is put forward, and the concrete scheme of digital signal synthesis based on FPGA in this transmitter is analyzed. The digital signal synthesis mainly includes digital up-conversion and signal synthesis at specific frequencies. The key technologies involved in the synthesis are analyzed in detail, such as low pass increment summation modulation, polar coordinate conversion and DDS digital phase modulation. The main results of this study are as follows: 1) the low pass incremental summation modulation technique involved is studied and designed. The modulation technology has the ability of noise reduction and anti-jamming. The first and second order increment summation modulators are modeled by SIMULINK based on MATLAB. The over-sampling rate OSR is all set to 12881 bit quantization. Finally, the simulation results show that the signal-to-noise ratio of the second order modulator is about 99 dB, and that of the first order modulator is about 73 dB, which is close to the value calculated directly from the signal-to-noise ratio formula. At the same time, comparing the spectrum of the two final output signals, the results show that the noise reduction effect of the second order modulator is obviously better than that of the first order, and the signal-to-noise ratio (SNR) is significantly improved by about 26 dB. 2) the polar coordinate conversion technology involved is studied and designed. The polar coordinate transformation of the modulated IQ signal is realized. First, we set the IQs signal as cosine and sine wave of frequency 5 Hz, and then we use MATLAB to simulate the polar diameter r is a constant. Conclusion .3) the DDS digital phase modulation technique is studied and designed to synthesize the signals with phase modulation and required frequency. First, the SIMULINK model is established, and the reference source cf is set to 125 MHz, phase accumulator bit N is 20, and the frequency control word K is selected to be 2 / 15 / 2 / 1 / 13 / 2 / 11 respectively for simulation, and the corresponding signal spectrum is obtained. The signal frequency obtained from the spectrum diagram is about 2.45 ~ 10 ~ 7 rad/s,6.14*10~6rad/s,1.53*10~6 rad/s, respectively, which satisfies the calculation formula of the synthetic signal frequency f _ s _ 0 K f_c/2~N. It is further proved that changing K can adjust the frequency value of the final synthetic signal of the DDS system. Secondly, the frequency of the final synthetic signal of the DDS system can be adjusted when the signal frequency is changed. The SIMULINK modeling and simulation of common 2PSK modulation technology are carried out by keying method and analog method, which lays a foundation for the simulation and verification of DDS digital phase modulation technology. Finally, the SIMULINK model of DDS digital phase modulation technology is established, and each parameter setting is the same as that of the previous DDS system. Taking only K 182 as an example to simulate, the 2PSK signal is output by setting the deflection phase signal of fixed period. The whole scheme of digital up-conversion and signal synthesis in the transmitter is realized in FPGA, finally downloaded to the FPGA development chip, and the output waveform of every key module is observed by using CHIPSCOPE software. The frequency of the output signal is about 21.4 MHz, which is similar to the frequency corresponding to the frequency control word K of 764504178, which verifies the rationality of the whole scheme.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN838

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 汪靜;單梁;萬實(shí);李軍;;動(dòng)態(tài)可重構(gòu)系統(tǒng)的CAN總線通信系統(tǒng)設(shè)計(jì)[J];工業(yè)控制計(jì)算機(jī);2015年02期

2 唐佑輝;黃騰;邱偉;王成;姚濤;;關(guān)于測(cè)量中平面坐標(biāo)系轉(zhuǎn)換的研究[J];勘察科學(xué)技術(shù);2014年05期

3 劉達(dá);韓曉冰;房龍;;3維直角坐標(biāo)系直接轉(zhuǎn)換算法的研究與實(shí)現(xiàn)[J];測(cè)繪與空間地理信息;2012年05期

4 保玲;佘世剛;周毅;金玉琳;;應(yīng)用于數(shù)字鎖相環(huán)的NCO設(shè)計(jì)[J];電子設(shè)計(jì)工程;2011年14期

5 曾博;楊志坤;;基于0.35μm工藝的Delta-Sigma ADC實(shí)現(xiàn)[J];電子設(shè)計(jì)工程;2010年02期

6 胡漢輝;譚青;;自適應(yīng)抗混疊濾波器在數(shù)據(jù)采集中的應(yīng)用[J];電測(cè)與儀表;2009年09期

7 楊廣琦;;微波毫米波技術(shù)研究與應(yīng)用前沿[J];國際學(xué)術(shù)動(dòng)態(tài);2009年01期

8 趙丹;方繼承;張世杰;于全;;頻率合成器對(duì)跳頻OFDM系統(tǒng)的性能影響分析[J];系統(tǒng)仿真學(xué)報(bào);2006年12期

9 王榮健;TD-SCDMA中軟件無線電技術(shù)的應(yīng)用[J];電信技術(shù);2005年05期

10 崔建鵬,趙敏,江帆;采用DDS技術(shù)實(shí)現(xiàn)的虛擬任意波形發(fā)生器[J];計(jì)算機(jī)測(cè)量與控制;2003年07期

相關(guān)碩士學(xué)位論文 前8條

1 鄭成波;基于SOPC技術(shù)的雷達(dá)數(shù)字接收機(jī)設(shè)計(jì)與實(shí)現(xiàn)[D];國防科學(xué)技術(shù)大學(xué);2011年

2 方奇;通信信號(hào)調(diào)制識(shí)別算法研究[D];國防科學(xué)技術(shù)大學(xué);2011年

3 李燕杰;小型多功能電荷校準(zhǔn)儀的設(shè)計(jì)[D];中北大學(xué);2010年

4 胡力堅(jiān);基于DDS的任意波形發(fā)生器設(shè)計(jì)與實(shí)現(xiàn)[D];西安電子科技大學(xué);2009年

5 喻峰;基于FPGA的低相噪DDS的設(shè)計(jì)與實(shí)現(xiàn)[D];哈爾濱工業(yè)大學(xué);2007年

6 郭立浩;基于FPGA的直接數(shù)字頻率合成器的研究與應(yīng)用[D];西北工業(yè)大學(xué);2006年

7 薛文;DDS任意波形發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)[D];南京理工大學(xué);2004年

8 李海;DDS綜合調(diào)制器的研究[D];西安電子科技大學(xué);2002年

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本文編號(hào)：2219986