基于FPGA的SPI與ⅡC總線通信系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間:2018-08-07 17:52
【摘要】:隨著數(shù)字集成電路的飛速發(fā)展,FPGA以其設(shè)計(jì)靈活、設(shè)計(jì)周期短、可靠性高等優(yōu)點(diǎn)受到越來越多的開發(fā)人員的追捧。除此之外,隨著現(xiàn)代科學(xué)技術(shù)的不斷進(jìn)步,人們對(duì)系統(tǒng)功能和性能的需求也在不斷的增長,這就對(duì)計(jì)算機(jī)與外圍設(shè)備之間的接口的性能提出了更高的要求。相對(duì)于并行總線來說,串行總線的性價(jià)比更高,在遠(yuǎn)距離數(shù)據(jù)傳輸方面具有無可替代的優(yōu)點(diǎn),故串行總線的應(yīng)用范圍也越來越廣泛,在多種器件上都集成有SPI總線或ⅡC總線的接口。但是在很多場(chǎng)合下,MCU本身并不具有SPI或ⅡC接口,這樣就使得數(shù)據(jù)的傳輸變得非常不方便。基于此,本文提出并設(shè)計(jì)了一種基于FPGA的SPI與ⅡC總線的通信系統(tǒng),利用這個(gè)系統(tǒng)能夠?qū)崿F(xiàn)SPI與ⅡC通信協(xié)議的相互轉(zhuǎn)換,使得SPI主設(shè)備與ⅡC從設(shè)備的通信、ⅡC主設(shè)備與SPI從設(shè)備的通信成為可能。本文首先簡(jiǎn)單介紹了整個(gè)通信系統(tǒng);然后分別針對(duì)SPI/ⅡC總線的具體性能要求,提出了基于FPGA的SPI/ⅡC總線的設(shè)計(jì)方案,并進(jìn)行了驗(yàn)證;最后根據(jù)設(shè)計(jì)要求及SPI/ⅡC總線的性能要求,提出了基于FPGA的SPI與ⅡC總線通信系統(tǒng)的設(shè)計(jì)方案,并對(duì)該方案進(jìn)行了軟件級(jí)的模擬仿真以及實(shí)驗(yàn)驗(yàn)證。本文中的設(shè)計(jì)方案將整個(gè)系統(tǒng)分成了 SPI總線、接口部分及ⅡC總線三部分,這使得整個(gè)設(shè)計(jì)結(jié)構(gòu)更加清晰。同時(shí)采用硬件描述語言VHDL編程,使其能夠在不同的應(yīng)用環(huán)境中進(jìn)行優(yōu)化,也能夠提高數(shù)據(jù)的傳輸速度。本文重點(diǎn)對(duì)通信系統(tǒng)的SPI總線、總線接口及ⅡC總線三部分進(jìn)行了研究,使用VHDL硬件描述語言完成了對(duì)其功能的描述,并得到了相應(yīng)的模塊圖,同時(shí)做了相應(yīng)的仿真及實(shí)驗(yàn)驗(yàn)證的工作,最后得到的仿真及實(shí)驗(yàn)結(jié)果基本符合設(shè)計(jì)要求。
[Abstract]:With the rapid development of digital integrated circuits, FPGA has been sought after by more and more developers for its advantages of flexible design, short design period and high reliability. In addition, with the continuous progress of modern science and technology, the demand for system function and performance is also increasing, which puts forward higher requirements for the performance of the interface between computer and peripheral equipment. Compared with parallel bus, serial bus has higher performance-to-price ratio and has irreplaceable advantages in long-distance data transmission, so the application of serial bus is more and more extensive. The interface of SPI bus or II C bus is integrated on many devices. However, in many cases, SPI itself does not have SPI or II C interface, which makes data transmission very inconvenient. Based on this, this paper proposes and designs a communication system between SPI and 鈪,
本文編號(hào):2170856
[Abstract]:With the rapid development of digital integrated circuits, FPGA has been sought after by more and more developers for its advantages of flexible design, short design period and high reliability. In addition, with the continuous progress of modern science and technology, the demand for system function and performance is also increasing, which puts forward higher requirements for the performance of the interface between computer and peripheral equipment. Compared with parallel bus, serial bus has higher performance-to-price ratio and has irreplaceable advantages in long-distance data transmission, so the application of serial bus is more and more extensive. The interface of SPI bus or II C bus is integrated on many devices. However, in many cases, SPI itself does not have SPI or II C interface, which makes data transmission very inconvenient. Based on this, this paper proposes and designs a communication system between SPI and 鈪,
本文編號(hào):2170856
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