寬帶數(shù)字接收機(jī)前端系統(tǒng)研究與設(shè)計
發(fā)布時間：2018-08-05 10:44
【摘要】：射頻前端系統(tǒng)作為接收機(jī)最重要的一部分,一直是無線接收機(jī)研究的重點,也是接收機(jī)實現(xiàn)較困難的部分之一。隨著數(shù)字處理技術(shù)的快速發(fā)展,數(shù)字電路在通信系統(tǒng)中比重越來越大。但是A/D轉(zhuǎn)換器直接量化采樣高頻信號還具有相當(dāng)?shù)碾y度,因此普遍利用前端系統(tǒng)將高頻信號下變頻到中頻再進(jìn)行中頻數(shù)字化的方案。射頻前端系統(tǒng)如何有效的接收有用信號,抑制無用信號對有用信號的干擾,一直是一個重要的研究課題。本論文擬設(shè)計適用于30-1200MHz寬帶數(shù)字接收機(jī)的前端系統(tǒng)電路,與普通通信接收機(jī)前端系統(tǒng)不同,本論文采用寬帶掃描式超外差接收機(jī)前端電路的設(shè)計路線。它的典型特征是具有一個寬帶捷變頻的本振和一個寬帶或可跟蹤的預(yù)選器。該前端系統(tǒng)采用兩次變頻的方案,引入了兩級混頻電路。為了實現(xiàn)寬帶數(shù)字接收機(jī)的掃描與分析功能,采取可變中頻的方案,即采用70MHz高中頻實現(xiàn)寬帶掃描功能,采用21.4MHz低中頻實現(xiàn)窄帶分析功能。為了實現(xiàn)接收機(jī)的高分辨率,本方案采用寬帶大步進(jìn)本振源1與窄帶小步進(jìn)本振源2組合控制的方案,并且利用串行接口完成快速配置,同時提供了控制芯片的關(guān)鍵代碼。本論文的撰寫工作按照實際課題先論證后設(shè)計的方法,主要設(shè)計工作包括以下三個部分:(1)利用二次變頻的超外差模型設(shè)計前端整體鏈路。結(jié)合工程實踐分析了設(shè)計思路,將系統(tǒng)指標(biāo)做分解。利用工程中實用的估算公式預(yù)算并驗證前端系統(tǒng)指標(biāo)需求。利用ADS軟件搭建前端電路鏈路等效模型,插入AC仿真控制器與增益控制模塊預(yù)算鏈路各功能模塊的增益狀態(tài),搭建頻率合成器鏈路模型預(yù)算了一本振等效電路的相位噪聲。(2)利用插入損耗法設(shè)計了一個截止頻率為1250MHz的橢圓函數(shù)微帶低通濾波器,用于濾除輸入信號的鏡像頻率和本振的反向輻射。采用階梯阻抗微帶濾波器模型,通過計算查詢橢圓函數(shù)歸一化表逆向算出微帶濾波器各枝節(jié)電長度,再通過AppCAD工具計算出物理尺寸,最后利用HFSS軟件建模仿真出S11、S21和VSWR曲線,得到插損、帶外抑制和駐波比等關(guān)鍵指標(biāo),再通過優(yōu)化處理得到了最優(yōu)的設(shè)計參數(shù)。(3)采用混頻環(huán)模型和DDS內(nèi)插鎖相環(huán)模型設(shè)計了兩個頻率合成器。本振源1利用Analog Device公司的ADF4151鑒相器和HITTITE公司的HMC440QS16G鑒相器設(shè)計了一個混頻環(huán)方案,實現(xiàn)了輸出頻率1560MHz-2730MHz步進(jìn)10MHz的雙環(huán)電路。本振源2利用ADF4002鑒相器和AD9915直接數(shù)字頻率合成器設(shè)計了一個DDS內(nèi)插環(huán)方案,實現(xiàn)了輸出頻率1450MHz-1518.6MHz步進(jìn)為1KHz的單環(huán)電路。在設(shè)計過程中將理論計算與工程實踐融合,詳細(xì)敘述了頻率合成器的設(shè)計原理與方法。其次利用ADIsimPLL、ADIsimDDS軟件仿真出頻域和時域的各項指標(biāo),最后在Altium Designer畫圖軟件設(shè)計原理圖和PCB圖紙,并給出最終的測試結(jié)果。
[Abstract]:As the most important part of the receiver, the RF front end system is always the focus of the wireless receiver, and is also one of the difficult parts of the receiver. With the rapid development of the digital processing technology, the proportion of digital circuits in the communication system is becoming more and more serious. But it is quite difficult to quantify the high frequency signal directly by the A/D converter. So it is an important research topic how the RF front end system receives the useful signal effectively and restraining the interference from the useful signal. This paper is designed to be used in the front of the 30-1200MHz wideband digital receiver. The end system circuit is different from the common communication receiver front-end system. This paper uses a broadband scanning ultra heterodyne receiver front-end circuit. Its typical feature is a broadband frequency agile local oscillator and a broadband or traceable preselector. The front end system uses two frequency conversion schemes and introduces two stage mixing power. In order to realize the scanning and analysis function of the wideband digital receiver, the scheme adopts the variable medium frequency scheme, that is, adopting the 70MHz high school frequency to realize the wideband scan function and using the 21.4MHz low IF frequency to realize the narrow band analysis function. In order to realize the high resolution of the receiver, this scheme uses the broadband and large step source 1 and the narrow band small step of the local oscillator source. In this paper, the main design work includes the following three parts: (1) design the whole link of the front end using the superheterodyne model of two frequency conversion. The design idea is analyzed and the system index is decomposed. The practical estimation formula in the project is used to budget and verify the index requirements of the front end system. The ADS software is used to build the equivalent model of the front-end circuit link, insert the AC simulation controller and the gain control module, and build the link model budget of the frequency synthesizer. Phase noise of an equivalent circuit. (2) an elliptic function microstrip low pass filter with cut-off frequency of 1250MHz is designed by insertion loss method, which is used to filter the image frequency of the input signal and the reverse radiation of the local oscillator. The step impedance microstrip filter model is used to reverse the micrograph of the calculated query ellipse function. With the power saving length of each branch of the filter, the physical size is calculated by AppCAD tool. Finally, S11, S21 and VSWR curves are simulated by HFSS software. The key parameters such as insertion loss, off band suppression and Bobbi are obtained, and the optimal design parameters are obtained by optimization. (3) the mixing loop model and DDS interpolated phase locked loop model are designed. Two frequency synthesizers. The source 1 uses Analog Device's ADF4151 phase detector and HITTITE's HMC440QS16G phase detector to design a mixing ring scheme, which realizes the double loop circuit of the output frequency 1560MHz-2730MHz step 10MHz. This oscillator 2 designs a DDS within a ADF4002 phase discriminator and a AD9915 direct digital frequency synthesizer. In the design process, the theoretical calculation and engineering practice are fused and the design principle and method of frequency synthesizer are described in detail. Secondly, the parameters of frequency domain and time domain are simulated by using ADIsimPLL and ADIsimDDS software, and finally in Altium Designer drawing. The software design schematic diagram and PCB drawings are given, and the final test results are given.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN858
[Abstract]:As the most important part of the receiver, the RF front end system is always the focus of the wireless receiver, and is also one of the difficult parts of the receiver. With the rapid development of the digital processing technology, the proportion of digital circuits in the communication system is becoming more and more serious. But it is quite difficult to quantify the high frequency signal directly by the A/D converter. So it is an important research topic how the RF front end system receives the useful signal effectively and restraining the interference from the useful signal. This paper is designed to be used in the front of the 30-1200MHz wideband digital receiver. The end system circuit is different from the common communication receiver front-end system. This paper uses a broadband scanning ultra heterodyne receiver front-end circuit. Its typical feature is a broadband frequency agile local oscillator and a broadband or traceable preselector. The front end system uses two frequency conversion schemes and introduces two stage mixing power. In order to realize the scanning and analysis function of the wideband digital receiver, the scheme adopts the variable medium frequency scheme, that is, adopting the 70MHz high school frequency to realize the wideband scan function and using the 21.4MHz low IF frequency to realize the narrow band analysis function. In order to realize the high resolution of the receiver, this scheme uses the broadband and large step source 1 and the narrow band small step of the local oscillator source. In this paper, the main design work includes the following three parts: (1) design the whole link of the front end using the superheterodyne model of two frequency conversion. The design idea is analyzed and the system index is decomposed. The practical estimation formula in the project is used to budget and verify the index requirements of the front end system. The ADS software is used to build the equivalent model of the front-end circuit link, insert the AC simulation controller and the gain control module, and build the link model budget of the frequency synthesizer. Phase noise of an equivalent circuit. (2) an elliptic function microstrip low pass filter with cut-off frequency of 1250MHz is designed by insertion loss method, which is used to filter the image frequency of the input signal and the reverse radiation of the local oscillator. The step impedance microstrip filter model is used to reverse the micrograph of the calculated query ellipse function. With the power saving length of each branch of the filter, the physical size is calculated by AppCAD tool. Finally, S11, S21 and VSWR curves are simulated by HFSS software. The key parameters such as insertion loss, off band suppression and Bobbi are obtained, and the optimal design parameters are obtained by optimization. (3) the mixing loop model and DDS interpolated phase locked loop model are designed. Two frequency synthesizers. The source 1 uses Analog Device's ADF4151 phase detector and HITTITE's HMC440QS16G phase detector to design a mixing ring scheme, which realizes the double loop circuit of the output frequency 1560MHz-2730MHz step 10MHz. This oscillator 2 designs a DDS within a ADF4002 phase discriminator and a AD9915 direct digital frequency synthesizer. In the design process, the theoretical calculation and engineering practice are fused and the design principle and method of frequency synthesizer are described in detail. Secondly, the parameters of frequency domain and time domain are simulated by using ADIsimPLL and ADIsimDDS software, and finally in Altium Designer drawing. The software design schematic diagram and PCB drawings are given, and the final test results are given.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN858
【參考文獻(xiàn)】
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