【摘要】：為了保證用戶的重要信息或數(shù)據(jù)在網(wǎng)絡(luò)與通信中不被未經(jīng)授權(quán)的第三方盜取,用戶需要將數(shù)據(jù)加密之后進(jìn)行通信。通常,最常用的數(shù)據(jù)加密方式是軟件加密,即在通用微處理器上編程實現(xiàn),但其加密速度普遍不高,算法實現(xiàn)的效率較低,安全性和可靠性有限,很多時候不能滿足用戶的需求。因此,需要更加快速,更加安全可靠的加密實現(xiàn)方式來滿足人們在一些場合下的數(shù)據(jù)保密要求�；贔PGA的加密算法實現(xiàn)具有安全性高,加密速度快,開發(fā)周期短,開發(fā)成本較低,可重配,可靠性高以及移植性好等優(yōu)點。所以,這種數(shù)據(jù)加密方式的獲得了越來越多的關(guān)注。本論文在研究AES(Advanced Encryption Standard)算法基本原理及其相關(guān)數(shù)學(xué)理論知識的基礎(chǔ)上,從四個方面對AES算法的FPGA硬件實現(xiàn)進(jìn)行優(yōu)化:首先,在總體設(shè)計上采用混合流水線結(jié)構(gòu):輪迭代間采用完全展開流水線結(jié)構(gòu),輪內(nèi)采用流水線結(jié)構(gòu);其次,字節(jié)替代與行移位組合實現(xiàn),減少行移位資源占用,字節(jié)替代,列混淆,密鑰拓展模塊使用查找表進(jìn)行優(yōu)化,降低運(yùn)算復(fù)雜度和資源占用,通過找出關(guān)鍵路徑并進(jìn)行優(yōu)化,再次提升加密速度;然后,加密過程與解密過程兩者共享密鑰拓擴(kuò)展模塊及查找替換表模塊,減少了可編程邏輯資源的消耗;最后,通過FPGA內(nèi)嵌的RAM(BRAM)預(yù)存查找表,從而進(jìn)一步減少FPGA芯片面積的消耗。對優(yōu)化后的AES算法進(jìn)行綜合、時序約束、布局布線,同時獲得資源消耗與工作頻率等參數(shù),并與同類研究進(jìn)行對比。結(jié)果證明,本設(shè)計實現(xiàn)了較快的加/解密速度,且資源消耗較低,在加/解密效率上有很大優(yōu)勢。在AES算法硬件實現(xiàn)優(yōu)化基礎(chǔ)上,利用自定制IP核技術(shù)將優(yōu)化后的AES算法封裝成IP軟核,以便于在任何FPGA芯片上復(fù)用。最后,在自定制AES IP核的基礎(chǔ)上,完成整個AES加/解密系統(tǒng)的設(shè)計。在專業(yè)仿真工具M(jìn)odelsim上仿真驗證AES加/解密系統(tǒng),然后使用Quartus II集成開發(fā)環(huán)境進(jìn)行綜合,布局布線,時序約束。最后下載到DE2開發(fā)板上進(jìn)行驗證,實驗結(jié)果表明AES加/解密系統(tǒng)可以正常且穩(wěn)定的運(yùn)行在200M的時鐘頻率下,加密速度可以達(dá)到6.4Gbit/s,可以滿足絕大多數(shù)的網(wǎng)絡(luò)或通信中的數(shù)據(jù)加密。整個系統(tǒng)結(jié)構(gòu)簡單,可自由配置功能模塊,安全性高,移植性好,便于實時維護(hù),可以廣泛的用于多種信息安全領(lǐng)域。
[Abstract]:In order to ensure that the important information or data of users are not stolen by unauthorized third parties in the network and communication, users need to encrypt the data and communicate. Usually, the most commonly used data encryption method is software encryption, that is, it is programmed on a general-purpose microprocessor, but its encryption speed is generally not high, the efficiency of the algorithm is low, and the security and reliability are limited. In many cases, it can not meet the needs of the user. Therefore, a faster, more secure and reliable encryption method is needed to meet the requirements of data security in some situations. The implementation of encryption algorithm based on FPGA has the advantages of high security, fast encryption speed, short development period, low development cost, rematch, high reliability and good portability. Therefore, this kind of data encryption method has gained more and more attention. On the basis of studying the basic principle of AES (Advanced Encryption Standard) algorithm and its related mathematical theory knowledge, this paper optimizes the FPGA hardware implementation of AES algorithm from four aspects: first of all, In the overall design, the hybrid pipeline structure is adopted: the fully expanded pipeline structure is adopted between wheel iterations, and the pipeline structure is adopted in the wheel; secondly, the combination of byte substitution and row shift is realized to reduce the resource occupation of row shift, byte substitution, column confusion, etc. Key expansion module uses lookup table to optimize, reduce computational complexity and resource occupation, by finding critical path and optimization, improve encryption speed again; then, The encryption process and decryption process share the key extension module and the lookup replacement table module to reduce the consumption of programmable logic resources. Finally, the area consumption of FPGA chip is further reduced by the RAM (BRAM) pre-stored lookup table embedded in FPGA. The optimized AES algorithm is synthesized, timing constraint, layout and routing, and the parameters such as resource consumption and working frequency are obtained, and compared with the similar research. The results show that the design achieves faster encryption / decryption speed and lower resource consumption, and has a great advantage in encryption / decryption efficiency. On the basis of hardware optimization of AES algorithm, the optimized AES algorithm is encapsulated into IP soft core by using custom IP kernel, which is easy to reuse on any FPGA chip. Finally, on the basis of custom AES IP core, the whole AES encryption / decryption system is designed. The AES encryption / decryption system is simulated and verified on the professional simulation tool Modelsim, and then the Quartus II integrated development environment is used for synthesis, layout, routing and timing constraints. The experimental results show that the AES encryption / decryption system can run normally and stably at 200m clock frequency, and the encryption speed can reach 6.4 Gbit / s, which can satisfy most of the data encryption in network or communication. The whole system has the advantages of simple structure, free configuration of function modules, high security, good portability, convenient real-time maintenance, and can be widely used in many kinds of information security fields.
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN918.4

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 張磊;武騰飛;申雅峰;;基于SOPC的光信號數(shù)據(jù)采集解調(diào)系統(tǒng)設(shè)計[J];光學(xué)技術(shù);2016年04期

2 曹珍富;;密碼學(xué)的新發(fā)展[J];四川大學(xué)學(xué)報(工程科學(xué)版);2015年01期

3 武一;郭婷婷;;基于FPGA的加密算法改進(jìn)及實現(xiàn)[J];電視技術(shù);2014年05期

4 鄭東;趙慶蘭;張應(yīng)輝;;密碼學(xué)綜述[J];西安郵電大學(xué)學(xué)報;2013年06期

5 王亮;顧美康;孫凱民;;針對AES加密算法的研究及其FPGA實現(xiàn)[J];電視技術(shù);2013年17期

6 殷偉鳳;;AES加密的資源優(yōu)化設(shè)計及FPGA實現(xiàn)[J];計算機(jī)與現(xiàn)代化;2012年11期

7 張勇;;初探網(wǎng)絡(luò)安全通信中的密碼學(xué)應(yīng)用[J];計算機(jī)安全;2011年03期

8 何德彪;胡進(jìn);陳建華;;基于FPGA的高速AES實現(xiàn)[J];華中科技大學(xué)學(xué)報(自然科學(xué)版);2010年02期

9 龔向東;黃虹賓;劉春平;;主從可配置I2C總線接口IP及其應(yīng)用[J];電訊技術(shù);2010年01期

10 呂游;劉剛;;AES算法的FPGA優(yōu)化實現(xiàn)[J];山西電子技術(shù);2007年01期

，

本文編號：2148541