【摘要】：為了保證用戶(hù)的重要信息或數(shù)據(jù)在網(wǎng)絡(luò)與通信中不被未經(jīng)授權(quán)的第三方盜取,用戶(hù)需要將數(shù)據(jù)加密之后進(jìn)行通信。通常,最常用的數(shù)據(jù)加密方式是軟件加密,即在通用微處理器上編程實(shí)現(xiàn),但其加密速度普遍不高,算法實(shí)現(xiàn)的效率較低,安全性和可靠性有限,很多時(shí)候不能滿(mǎn)足用戶(hù)的需求。因此,需要更加快速,更加安全可靠的加密實(shí)現(xiàn)方式來(lái)滿(mǎn)足人們?cè)谝恍﹫?chǎng)合下的數(shù)據(jù)保密要求�；贔PGA的加密算法實(shí)現(xiàn)具有安全性高,加密速度快,開(kāi)發(fā)周期短,開(kāi)發(fā)成本較低,可重配,可靠性高以及移植性好等優(yōu)點(diǎn)。所以,這種數(shù)據(jù)加密方式的獲得了越來(lái)越多的關(guān)注。本論文在研究AES(Advanced Encryption Standard)算法基本原理及其相關(guān)數(shù)學(xué)理論知識(shí)的基礎(chǔ)上,從四個(gè)方面對(duì)AES算法的FPGA硬件實(shí)現(xiàn)進(jìn)行優(yōu)化:首先,在總體設(shè)計(jì)上采用混合流水線(xiàn)結(jié)構(gòu):輪迭代間采用完全展開(kāi)流水線(xiàn)結(jié)構(gòu),輪內(nèi)采用流水線(xiàn)結(jié)構(gòu);其次,字節(jié)替代與行移位組合實(shí)現(xiàn),減少行移位資源占用,字節(jié)替代,列混淆,密鑰拓展模塊使用查找表進(jìn)行優(yōu)化,降低運(yùn)算復(fù)雜度和資源占用,通過(guò)找出關(guān)鍵路徑并進(jìn)行優(yōu)化,再次提升加密速度;然后,加密過(guò)程與解密過(guò)程兩者共享密鑰拓?cái)U(kuò)展模塊及查找替換表模塊,減少了可編程邏輯資源的消耗;最后,通過(guò)FPGA內(nèi)嵌的RAM(BRAM)預(yù)存查找表,從而進(jìn)一步減少FPGA芯片面積的消耗。對(duì)優(yōu)化后的AES算法進(jìn)行綜合、時(shí)序約束、布局布線(xiàn),同時(shí)獲得資源消耗與工作頻率等參數(shù),并與同類(lèi)研究進(jìn)行對(duì)比。結(jié)果證明,本設(shè)計(jì)實(shí)現(xiàn)了較快的加/解密速度,且資源消耗較低,在加/解密效率上有很大優(yōu)勢(shì)。在AES算法硬件實(shí)現(xiàn)優(yōu)化基礎(chǔ)上,利用自定制IP核技術(shù)將優(yōu)化后的AES算法封裝成IP軟核,以便于在任何FPGA芯片上復(fù)用。最后,在自定制AES IP核的基礎(chǔ)上,完成整個(gè)AES加/解密系統(tǒng)的設(shè)計(jì)。在專(zhuān)業(yè)仿真工具M(jìn)odelsim上仿真驗(yàn)證AES加/解密系統(tǒng),然后使用Quartus II集成開(kāi)發(fā)環(huán)境進(jìn)行綜合,布局布線(xiàn),時(shí)序約束。最后下載到DE2開(kāi)發(fā)板上進(jìn)行驗(yàn)證,實(shí)驗(yàn)結(jié)果表明AES加/解密系統(tǒng)可以正常且穩(wěn)定的運(yùn)行在200M的時(shí)鐘頻率下,加密速度可以達(dá)到6.4Gbit/s,可以滿(mǎn)足絕大多數(shù)的網(wǎng)絡(luò)或通信中的數(shù)據(jù)加密。整個(gè)系統(tǒng)結(jié)構(gòu)簡(jiǎn)單,可自由配置功能模塊,安全性高,移植性好,便于實(shí)時(shí)維護(hù),可以廣泛的用于多種信息安全領(lǐng)域。
[Abstract]:In order to ensure that the important information or data of users are not stolen by unauthorized third parties in the network and communication, users need to encrypt the data and communicate. Usually, the most commonly used data encryption method is software encryption, that is, it is programmed on a general-purpose microprocessor, but its encryption speed is generally not high, the efficiency of the algorithm is low, and the security and reliability are limited. In many cases, it can not meet the needs of the user. Therefore, a faster, more secure and reliable encryption method is needed to meet the requirements of data security in some situations. The implementation of encryption algorithm based on FPGA has the advantages of high security, fast encryption speed, short development period, low development cost, rematch, high reliability and good portability. Therefore, this kind of data encryption method has gained more and more attention. On the basis of studying the basic principle of AES (Advanced Encryption Standard) algorithm and its related mathematical theory knowledge, this paper optimizes the FPGA hardware implementation of AES algorithm from four aspects: first of all, In the overall design, the hybrid pipeline structure is adopted: the fully expanded pipeline structure is adopted between wheel iterations, and the pipeline structure is adopted in the wheel; secondly, the combination of byte substitution and row shift is realized to reduce the resource occupation of row shift, byte substitution, column confusion, etc. Key expansion module uses lookup table to optimize, reduce computational complexity and resource occupation, by finding critical path and optimization, improve encryption speed again; then, The encryption process and decryption process share the key extension module and the lookup replacement table module to reduce the consumption of programmable logic resources. Finally, the area consumption of FPGA chip is further reduced by the RAM (BRAM) pre-stored lookup table embedded in FPGA. The optimized AES algorithm is synthesized, timing constraint, layout and routing, and the parameters such as resource consumption and working frequency are obtained, and compared with the similar research. The results show that the design achieves faster encryption / decryption speed and lower resource consumption, and has a great advantage in encryption / decryption efficiency. On the basis of hardware optimization of AES algorithm, the optimized AES algorithm is encapsulated into IP soft core by using custom IP kernel, which is easy to reuse on any FPGA chip. Finally, on the basis of custom AES IP core, the whole AES encryption / decryption system is designed. The AES encryption / decryption system is simulated and verified on the professional simulation tool Modelsim, and then the Quartus II integrated development environment is used for synthesis, layout, routing and timing constraints. The experimental results show that the AES encryption / decryption system can run normally and stably at 200m clock frequency, and the encryption speed can reach 6.4 Gbit / s, which can satisfy most of the data encryption in network or communication. The whole system has the advantages of simple structure, free configuration of function modules, high security, good portability, convenient real-time maintenance, and can be widely used in many kinds of information security fields.
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TN918.4

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本文編號(hào)：2148541