本文選題：DDS + FPGA��； 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：雷達(dá)信號(hào)發(fā)生器是雷達(dá)回波信號(hào)模擬器的核心組件,隨著雷達(dá)技術(shù)在工業(yè)應(yīng)用及民用上的普及和微電子技術(shù)的快速發(fā)展,雷達(dá)信號(hào)發(fā)生器的使用環(huán)境、場(chǎng)合越來(lái)越復(fù)雜,雷達(dá)信號(hào)發(fā)生器需要產(chǎn)生的雷達(dá)回波信號(hào)種類、回波信號(hào)的質(zhì)量要求也越來(lái)越高。為了滿足雷達(dá)回波模擬器的需求,本論文采用FPGA+DDS的實(shí)現(xiàn)結(jié)構(gòu)設(shè)計(jì)了一款基于DDS的復(fù)雜雷達(dá)信號(hào)發(fā)生器。本論文首先對(duì)雷達(dá)信號(hào)發(fā)生器的功能及性能要求進(jìn)行分析,介紹了本課題設(shè)計(jì)的雷達(dá)信號(hào)發(fā)生器所需要達(dá)到的指標(biāo)要求。針對(duì)這些指標(biāo)要求對(duì)雷達(dá)信號(hào)發(fā)生器功能部分進(jìn)行細(xì)分,拆分系統(tǒng)結(jié)構(gòu)、細(xì)化設(shè)計(jì),最終將系統(tǒng)劃分為核心模塊及控制模塊兩個(gè)功能模塊。核心模塊實(shí)現(xiàn)雷達(dá)信號(hào)產(chǎn)生,控制模塊負(fù)責(zé)雷達(dá)信號(hào)產(chǎn)生的控制及系統(tǒng)其它功能實(shí)現(xiàn)。在完成系統(tǒng)方案分析及設(shè)計(jì)的基礎(chǔ)上,本論文完成了基于DDS的復(fù)雜雷達(dá)信號(hào)發(fā)生器的硬件電路設(shè)計(jì)及邏輯設(shè)計(jì)。硬件電路設(shè)計(jì)部分分為控制模塊及核心模塊硬件電路,兩部分硬件電路主要由FPGA電路、電源電路、DDS電路、信號(hào)通路電路等組成,本文詳細(xì)介紹了FPGA選型、DDS電路設(shè)計(jì)、電源電路設(shè)計(jì)。邏輯設(shè)計(jì)主要由雷達(dá)信號(hào)發(fā)生器控制及通信邏輯、雷達(dá)信號(hào)產(chǎn)生邏輯組成,控制及通信邏輯包含控制模塊邏輯及核心模塊部分控制邏輯,雷達(dá)信號(hào)產(chǎn)生邏輯為本文設(shè)計(jì)核心。本文從DDS產(chǎn)生雷達(dá)信號(hào)原理、DDS產(chǎn)生雷達(dá)信號(hào)實(shí)現(xiàn)方式兩個(gè)方面詳細(xì)介紹雷達(dá)信號(hào)產(chǎn)生邏輯的設(shè)計(jì)及實(shí)現(xiàn)。在本文中還將拓展核心模塊功能的設(shè)計(jì),使核心模塊的使用不再局限于本系統(tǒng)中。隨后,本論文介紹了系統(tǒng)的調(diào)試方法。系統(tǒng)的調(diào)試包括硬件電路板的調(diào)試及邏輯設(shè)計(jì)的調(diào)試,最后還要進(jìn)行系統(tǒng)功能及性能的調(diào)試驗(yàn)證。經(jīng)過(guò)對(duì)整個(gè)系統(tǒng)的調(diào)試驗(yàn)證,本文設(shè)計(jì)的基于DDS的復(fù)雜雷達(dá)信號(hào)發(fā)生器,滿足設(shè)計(jì)性能及功能要求,達(dá)到了設(shè)計(jì)預(yù)期的目標(biāo)。經(jīng)過(guò)對(duì)整個(gè)系統(tǒng)設(shè)計(jì)的分析,基于DDS結(jié)構(gòu)的雷達(dá)信號(hào)發(fā)生器在實(shí)現(xiàn)線性調(diào)頻信號(hào)、頻率捷變、頻率跳變方面比傳統(tǒng)雷達(dá)信號(hào)發(fā)生器優(yōu)勢(shì)突出。
[Abstract]:Radar signal generator is the core component of radar echo signal simulator. With the popularization of radar technology in industry and civil use and the rapid development of microelectronic technology, the application environment of radar signal generator is becoming more and more complicated. The types of radar echo signals needed to be generated by radar signal generators and the quality requirements of echo signals are becoming more and more high. In order to meet the requirement of radar echo simulator, a complex radar signal generator based on FPGA DDS is designed in this paper. In this paper, the function and performance requirements of radar signal generator are analyzed, and the requirements of radar signal generator designed in this paper are introduced. According to these indexes, the function part of radar signal generator is subdivided, the structure of the system is split and the design is refined. Finally, the system is divided into two functional modules: the core module and the control module. The core module realizes radar signal generation, and the control module is responsible for radar signal generation control and other functions of the system. Based on the analysis and design of the system scheme, the hardware circuit design and logic design of the complex radar signal generator based on DDS are completed in this paper. The hardware circuit design is divided into control module and core module hardware circuit. The two parts of hardware circuit are mainly composed of FPGA circuit, power supply circuit DDS circuit, signal path circuit, etc. In this paper, the design of FPGA type selection DDS circuit is introduced in detail. Power circuit design. Logic design mainly consists of radar signal generator control and communication logic, radar signal generation logic, control and communication logic including control module logic and core module control logic, radar signal generation logic is the core of this design. This paper introduces the design and implementation of radar signal generation logic in detail from two aspects: the principle of DDS generation radar signal and the realization mode of DDS signal generation. In this paper, we will expand the design of the core module function, so that the use of the core module is no longer limited to the system. Then, this paper introduces the debugging method of the system. The debugging of the system includes the debugging of the hardware circuit board and the logic design, and the debugging of the system function and performance. After the debugging and verification of the whole system, the complex radar signal generator based on DDS is designed in this paper, which meets the design performance and function requirements, and achieves the desired goal. Through the analysis of the whole system design, the radar signal generator based on DDS structure is superior to the traditional radar signal generator in the realization of linear frequency modulation signal, frequency agility and frequency jump.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN957

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 潘添翼;劉太君;劉麗;陳薇;龍丹桂;;X波段LFMCW雷達(dá)頻率源的設(shè)計(jì)與實(shí)現(xiàn)[J];固體電子學(xué)研究與進(jìn)展;2015年06期

2 顏福才;;按鍵消抖電路瞬態(tài)分析和設(shè)計(jì)[J];現(xiàn)代電子技術(shù);2014年06期

3 曾飛;周聶;;橢圓函數(shù)低通濾波器及其在微波頻綜中的應(yīng)用[J];壓電與聲光;2011年06期

4 李學(xué)鋒;權(quán)赫;;基于隔離帶方法的兩平行微帶線間串?dāng)_抑制分析[J];計(jì)算機(jī)測(cè)量與控制;2011年09期

5 鄒國(guó)平;崔翔;魏興昌;李爾平;;高速電路電源/地層間阻抗參數(shù)計(jì)算與分析[J];電波科學(xué)學(xué)報(bào);2011年02期

6 劉偉;鐘子發(fā);葉春逢;;基于FPGA+DDS的信號(hào)源設(shè)計(jì)與實(shí)現(xiàn)[J];微型機(jī)與應(yīng)用;2010年18期

7 俞興明;;正弦信號(hào)發(fā)生器的DSP實(shí)現(xiàn)方法及比較[J];福建電腦;2009年09期

8 王兵;;頻率合成技術(shù)發(fā)展淺析[J];電子信息對(duì)抗技術(shù);2009年03期

9 王玉華;管愛紅;侯志強(qiáng);詹靜;張煥國(guó);;基于LFSR的演化隨機(jī)序列發(fā)生器[J];計(jì)算機(jī)工程;2009年06期

10 亦光;;電源IC發(fā)展趨勢(shì)綜述[J];電子測(cè)試;2007年12期

相關(guān)會(huì)議論文 前1條

1 趙擁軍;;新一代雷達(dá)系統(tǒng)的測(cè)試[A];21世紀(jì)中國(guó)電子儀器發(fā)展戰(zhàn)略研討會(huì)文集[C];2004年

相關(guān)碩士學(xué)位論文 前5條

1 劉聰;低雜散寬帶直接數(shù)字頻率合成技術(shù)研究[D];北京理工大學(xué);2014年

2 嚴(yán)湘南;雷達(dá)目標(biāo)與環(huán)境回波信號(hào)仿真系統(tǒng)設(shè)計(jì)與開發(fā)[D];西安電子科技大學(xué);2013年

3 程海濱;陣列DDS雜散抑制技術(shù)研究[D];電子科技大學(xué);2010年

4 姜心潛;雷達(dá)中頻模擬器[D];南京理工大學(xué);2009年

5 趙蘭;L波段高頻率分辨率微波頻率源的研究[D];華東師范大學(xué);2008年

，

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