基于CORDIC算法的BLE4.0發(fā)射機數(shù)字基帶的設(shè)計與實現(xiàn)
發(fā)布時間:2018-07-05 04:41
本文選題:藍牙4.0 + 數(shù)字基帶; 參考:《東南大學》2016年碩士論文
【摘要】:藍牙4.0擁有低功耗、低成本等特點,故其在短距離無線通信領(lǐng)域中得到廣泛的應(yīng)用。隨著社會的不斷進步,低功耗藍牙數(shù)字基帶也變得越來越重要,因此,設(shè)計一種復雜度低和資源消耗少的低功耗藍牙發(fā)射機數(shù)字基帶電路具有重要意義。本文設(shè)計了一種實現(xiàn)藍牙4.0發(fā)射機數(shù)字基帶電路的方案。該方案針對CORDIC算法中迭代次數(shù)過多的問題,在免縮放因子CORDIC算法的基礎(chǔ)上使用了區(qū)間折疊技術(shù),通過區(qū)域映射,可以真正的避免對縮放因子的計算,同時又可以快速的計算輸入角度,以達到減少迭代次數(shù)的目的,從而減少資源的消耗。另外,為了簡化運算過程,在這種方案實施之前,采用了區(qū)域映射,將不同區(qū)域的角度映射到[0,pi/4]。完成各模塊的設(shè)計后,在本文的最后,搭建了FPGA平臺對發(fā)射機數(shù)字基帶電路系統(tǒng)進行了仿真驗證。FPGA驗證的結(jié)果表明:在8MHz的系統(tǒng)時鐘下,所設(shè)計的發(fā)射機數(shù)字基帶電路能夠?qū)崿F(xiàn)碼率為1Mbps的信號,發(fā)射機數(shù)字基帶電路中高斯頻移鍵控(GFSK)調(diào)制信號的均方根誤差約為4.305%,改進后的CORDIC模塊與傳統(tǒng)的實現(xiàn)方式相比,邏輯資源消耗減少了16.5%。本文設(shè)計的藍牙4.0發(fā)射機數(shù)字基帶電路在性能上能夠很好的符合系統(tǒng)指標要求,為低功耗藍牙發(fā)射機數(shù)字基帶電路的設(shè)計提供了參考,具有一定的應(yīng)用前景和實用價值。
[Abstract]:Bluetooth 4.0 has the characteristics of low power consumption and low cost, so it is widely used in short range wireless communication field. With the development of society, low-power Bluetooth digital baseband becomes more and more important. Therefore, it is important to design a low-power Bluetooth transmitter digital baseband circuit with low complexity and low resource consumption. In this paper, a scheme of realizing the digital baseband circuit of Bluetooth 4.0 transmitter is designed. Aiming at the problem of too many iterations in Cordic algorithm, this scheme uses interval folding technology on the basis of non-scaling factor Cordic algorithm. By means of region mapping, the calculation of scaling factor can be avoided. At the same time, the input angle can be calculated quickly to reduce the number of iterations and reduce the consumption of resources. In addition, in order to simplify the operation process, the region mapping is adopted before the implementation of this scheme, and the angle of different regions is mapped to [0 pip / 4]. At the end of this paper, the FPGA platform is built to verify the transmitter digital baseband circuit system. The results of FPGA verification show that: under the system clock of 8 MHz, The designed transmitter digital baseband circuit can realize the signal with code rate of 1Mbps. The root mean square error of the Gao Si frequency shift keying modulation signal in the transmitter digital baseband circuit is about 4.305. The improved Cordic module is compared with the traditional implementation mode. Logical resource consumption was reduced by 16.5. The digital baseband circuit of Bluetooth transmitter 4.0 designed in this paper can meet the requirements of the system well in performance, which provides a reference for the design of digital baseband circuit of low power Bluetooth transmitter, and has a certain application prospect and practical value.
【學位授予單位】:東南大學
【學位級別】:碩士
【學位授予年份】:2016
【分類號】:TN83
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1 鎮(zhèn)咸舜;藍牙低功耗技術(shù)的研究與實現(xiàn)[D];華東師范大學;2013年
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