發(fā)布時(shí)間：2018-06-28 10:38

  本文選題：視頻圖像采集 + 視頻圖像預(yù)處理�。� 參考：《西安理工大學(xué)》2017年碩士論文

【摘要】：圖像的高速采集與實(shí)時(shí)處理在國(guó)防軍事、工業(yè)控制、安全防控等領(lǐng)域具有十分重要的應(yīng)用價(jià)值。而現(xiàn)場(chǎng)可編程門陣列(FPGA)以其集成度高、應(yīng)用靈活、設(shè)計(jì)周期短、開發(fā)成本低等特點(diǎn),廣泛地應(yīng)用在視頻圖像采集與處理領(lǐng)域。FPGA的并行處理能力與流水線作業(yè)能顯著地提高視頻圖像處理的速度,因此基于FPGA的系統(tǒng)設(shè)計(jì)成為圖像采集與處理領(lǐng)域的主流解決方案。首先確定了基于FPGA的視頻圖像采集與預(yù)處理系統(tǒng)的設(shè)計(jì)方案。系統(tǒng)主要由圖像采集和圖像預(yù)處理兩大部分組成。在圖像采集部分中,CCD圖像傳感器輸出模擬CVBS信號(hào),經(jīng)視頻解碼芯片ADV7181B將模擬信號(hào)轉(zhuǎn)換成數(shù)字信號(hào),再通過(guò)視頻解碼模塊將其解碼成CCIR656 YCbCr4:2:2格式的數(shù)據(jù)信號(hào),然后利用乒乓操作輪流的存儲(chǔ)在兩片SDRAM中。在圖像預(yù)處理部分中,詳細(xì)論述了 Sobel邊緣檢測(cè)算法和形態(tài)學(xué)濾波算法的運(yùn)算原理,以及圖像邊緣檢測(cè)與輪廓提取的實(shí)現(xiàn)方法,采用色度空間轉(zhuǎn)換將YCbCr4:2:2格式數(shù)據(jù)轉(zhuǎn)換成RGB格式通過(guò)VGA接口顯示。使用VerilogHDL完成基于FPGA的I2C配置模塊、視頻解碼模塊、SDRAM控制模塊、圖像預(yù)處理模塊、VGA顯示接口模塊等硬件電路設(shè)計(jì)。在Modelsim中對(duì)各個(gè)模塊進(jìn)行了仿真驗(yàn)證,然后將這些模塊構(gòu)成的系統(tǒng)頂層設(shè)計(jì)文件,經(jīng)Altera公司的Quartus Ⅱ 13.0環(huán)境編譯后,下載到開發(fā)板進(jìn)行實(shí)驗(yàn),結(jié)果證明了設(shè)計(jì)方案的可行性和正確性,達(dá)到預(yù)期的設(shè)計(jì)目的。
[Abstract]:High-speed image acquisition and real-time processing have important application value in the field of national defense, industrial control, safety control and so on. Field Programmable Gate Array (FPGA) is characterized by its high integration, flexible application, short design period and low development cost. The parallel processing ability and pipelining of FPGA are widely used in the field of video image acquisition and processing, so the system design based on FPGA has become the mainstream solution in the field of image acquisition and processing. Firstly, the design scheme of video image acquisition and preprocessing system based on FPGA is determined. The system consists of two parts: image acquisition and image preprocessing. In the part of image acquisition, CCD image sensor outputs analog CVBS signal. The analog signal is converted into digital signal by video decoding chip ADV7181B, and then decoded into CCIR656 YCbCr4: 2: 2: 2 data signal by video decoding module. Then the ping-pong operation is stored in two pieces of SDRAM in turn. In the part of image preprocessing, the operation principle of Sobel edge detection algorithm and morphological filter algorithm is discussed in detail, as well as the realization method of image edge detection and contour extraction. The YCbCr4: 2: 2 format data is transformed into RGB format by color space conversion. I 2C configuration module based on FPGA, video decoding module SDRAM control module, image preprocessing module and VGA display interface module are designed with Verilog HDL. Each module is simulated and verified in Modelsim, and then the top-level design file of the system is compiled by Quartus 鈪，

本文編號(hào)：2077714