本文選題：橢圓曲線(xiàn)密碼 + 專(zhuān)用指令處理器��； 參考：《計(jì)算機(jī)學(xué)報(bào)》2017年05期

【摘要】：與其他公鑰密碼算法相比,橢圓曲線(xiàn)密碼算法(Elliptic Curve Cryptography,ECC)具有抗攻擊能力強(qiáng)、計(jì)算量小以及處理速度快等優(yōu)點(diǎn),已成為下一代公鑰密碼體制的標(biāo)準(zhǔn).隨著ECC在嵌入式領(lǐng)域的應(yīng)用日益廣泛,如何提高其執(zhí)行效率成為目前研究的熱點(diǎn)問(wèn)題.文中提出了一套通用的專(zhuān)用指令處理器(Application Specific Instruction Processor,ASIP)的設(shè)計(jì)驗(yàn)證方案,并將該方案應(yīng)用于ECC,從而大幅提升其在硬件資源受限的嵌入式環(huán)境中的執(zhí)行效率.首先借鑒并實(shí)現(xiàn)了OpenSSL公開(kāi)的ECC軟件優(yōu)化方案,并結(jié)合處理器平臺(tái)的特點(diǎn)對(duì)大整數(shù)乘法運(yùn)算和多項(xiàng)式平方運(yùn)算進(jìn)行了進(jìn)一步優(yōu)化.其次對(duì)優(yōu)化后的算法進(jìn)行基本指令塊(Basic Instruction Block,BIB)的劃分并轉(zhuǎn)化為數(shù)據(jù)流圖(Data Flow Graph,DFG),在DFG圖中依照專(zhuān)用指令設(shè)計(jì)規(guī)則引入近似最優(yōu)解方法查找可優(yōu)化指令塊.對(duì)該類(lèi)指令塊設(shè)計(jì)相應(yīng)的專(zhuān)用指令,以實(shí)現(xiàn)處理器原有基礎(chǔ)指令集架構(gòu)的擴(kuò)展.再次基于電子系統(tǒng)級(jí)(Electronic System Level,ESL)設(shè)計(jì)方法依次設(shè)計(jì)并仿真驗(yàn)證ECC_ASIP的系統(tǒng)級(jí)模型和Verilog寄存器傳輸級(jí)(Register Transfer Level,RTL)模型.最后將驗(yàn)證通過(guò)的RTL級(jí)處理器模型進(jìn)行綜合、布局布線(xiàn),轉(zhuǎn)換成相對(duì)應(yīng)的門(mén)級(jí)電路并統(tǒng)計(jì)模型使用的硬件資源信息,燒寫(xiě)到FPGA(Field-Programmable Gate Array)平臺(tái)完成ECC_ASIP的移植操作和性能驗(yàn)證.與ARM11處理器平臺(tái)下算法實(shí)現(xiàn)的性能表現(xiàn)進(jìn)行對(duì)比,實(shí)驗(yàn)結(jié)果顯示,ECC_ASIP犧牲了9.23x%的硬件擴(kuò)展資源,將算法實(shí)現(xiàn)的運(yùn)算速度提高了2.74x倍,指令代碼存儲(chǔ)空間減少了59.36x%.
[Abstract]:Compared with other public key cryptography algorithms, Elliptic Curve Cryptograph ECC (ECC) has become the standard of the next generation public key cryptosystem because of its strong anti-attack ability, small computation and fast processing speed. With the increasing application of ECC in embedded field, how to improve its execution efficiency has become a hot issue. In this paper, a design and verification scheme of Application specific instruction processor (ASIP) is proposed, and the scheme is applied to Ecc, which greatly improves its execution efficiency in embedded environment with limited hardware resources. The ECC software optimization scheme published by OpenSSL is first used for reference and implemented, and the large integer multiplication and polynomial square operation are further optimized according to the characteristics of the processor platform. Secondly, the optimized algorithm is divided into basic instruction block (BIB) and transformed into data flow graph (DFG). According to the special instruction design rules, the approximate optimal solution method is introduced to find the optimized instruction block in the DFG diagram. The corresponding special instructions are designed to implement the extension of the original basic instruction set architecture of the processor. Based on the design method of Electronic system level ESL (Electronic system level ESL), the system level model and Register transfer level RTL model of ECCS ASIP are designed and simulated. Finally, the verified RTL-level processor model is synthesized, wired, converted into the corresponding gate circuit, and the hardware resource information used by the model is counted, and written to the FPGA (Field-Programmable Gate Array) platform to complete the porting operation and performance verification of ECCSIP. Compared with the performance of the algorithm implemented on ARM11 processor platform, the experimental results show that ECCS ASIP sacrificed 9.23x% of hardware extension resources, increased the speed of the algorithm by 2.74x, and reduced the storage space of instruction code by 59.36x.
【作者單位】： 青島大學(xué)計(jì)算機(jī)科學(xué)技術(shù)學(xué)院;青島大學(xué)系統(tǒng)科學(xué)博士后流動(dòng)站自動(dòng)化與電氣工程學(xué)院;山東大學(xué)山東省軟件工程重點(diǎn)實(shí)驗(yàn)室;中國(guó)科學(xué)院信息工程研究所信息安全國(guó)家重點(diǎn)實(shí)驗(yàn)室;
【基金】：國(guó)家自然科學(xué)基金(61402245,61572267,61272425,61170106,11472144) 國(guó)家科技支撐計(jì)劃子課題(2014BAG03B05) “十二五”國(guó)家密碼發(fā)展基金(MMJJ201301011) 中國(guó)博士后科學(xué)基金第八批特別資助(2015T80696);中國(guó)博士后科學(xué)基金面上項(xiàng)目(2014M551870) 山東省自然科學(xué)基金(ZR2014FQ010) 青島市博士后應(yīng)用研究項(xiàng)目 山東省軟件工程重點(diǎn)實(shí)驗(yàn)室開(kāi)放課題(2013SE01)資助~~
【分類(lèi)號(hào)】：TN918.4

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