實時數(shù)據(jù)包重組及多協(xié)議傳輸技術研究
發(fā)布時間:2018-06-19 06:21
本文選題:實時數(shù)據(jù)重組 + 多協(xié)議傳輸; 參考:《浙江大學》2017年碩士論文
【摘要】:處理器的計算能力越來越強,各種嵌入式計算平臺也是層出不窮。不同平臺間的實時通信協(xié)議變得多種多樣,如RocketIO、PCIe和光纖通道(Fibre Channel,FC)等。為了促進不同系統(tǒng)平臺間的高速互連,研究實時數(shù)據(jù)包重組和多協(xié)議傳輸技術具有非常重要的意義和現(xiàn)實價值。本文主要目標為設計支持PCIe、RocketIO、FC三種通信協(xié)議的嵌入式系統(tǒng),實現(xiàn)PCIe與RocketIO、PCIe與FC協(xié)議之間數(shù)據(jù)包實時重組和傳輸?shù)墓δ。本文在深入研究FC、PCIe、RocketIO三種通信協(xié)議特征的基礎上,提出了針對這三種協(xié)議傳輸?shù)臄?shù)據(jù)格式與轉換機制。此外,本文還設計了自定義控制信息數(shù)據(jù)包,實現(xiàn)了對PCIe轉FC、PCIe轉RocketIO動態(tài)重構和傳輸協(xié)議動態(tài)切換。然后,本文在高性能硬件FPGA平臺上設計了數(shù)據(jù)包按地址區(qū)分接收模塊、DDR存儲控制模塊、數(shù)據(jù)流控和組包模塊,完成了協(xié)議間的數(shù)據(jù)包重組功能,建立了PCIe協(xié)議和RocketIO協(xié)議、FC協(xié)議和PCIe協(xié)議互相轉換的通路,并支持FC網(wǎng)絡登陸認證和網(wǎng)絡管理功能。最后,本文對設計的模塊進行了仿真和實測,對數(shù)據(jù)包實時重組和傳輸系統(tǒng)的功能和性能進行了驗證。最終仿真和測試結果表明:PCIe數(shù)據(jù)包能夠高效的實時重組和通過RocketIO協(xié)議發(fā)送出去;RocketIO轉PCIe速率為240MB/s。PCIe數(shù)據(jù)包轉化成FC幀發(fā)送,帶寬可達382.34MB/s。PCIe轉FC、PCIe轉RocketIO兩種功能可在自定義控制信息控制下實現(xiàn)動態(tài)切換。
[Abstract]:The computing power of processors is becoming stronger and stronger, and various embedded computing platforms are emerging in endlessly. Real time communication protocols between different platforms such as RocketION PCIe and fiber channel fibre Channel (FC) have become diverse. In order to promote the high speed interconnection between different system platforms, it is of great significance and practical value to study the technologies of real-time packet reassembly and multi-protocol transmission. The main goal of this paper is to design an embedded system that supports three kinds of communication protocols of PCIe RocketIOF FC, and realize the function of real time data packet recombination and transmission between PCIe and RocketION PCIe and FC protocol. On the basis of deeply studying the characteristics of three kinds of communication protocols, the data format and conversion mechanism for these three protocols are put forward in this paper. In addition, this paper also designs the self-defined control information packet, realizes the dynamic reconfiguration of PCIe to FCU PCIe to RocketIO and the dynamic switching of transmission protocol. Then, this paper designs DDR storage control module, data flow control module and packet formation module on high performance FPGA platform. The PCIe protocol and RocketIO protocol, FC protocol and PCIe protocol conversion path are established, and FC network login authentication and network management functions are supported. Finally, the module is simulated and measured, and the function and performance of the real time data packet recombination and transmission system are verified. The final simulation and test results show that the 1: PCIe packet can be efficiently reorganized in real time and sent out through RocketIO protocol. The rate of RocketIO to PCIe is 240MB / s. PCIe data packet is converted into FC frame transmission. The bandwidth can reach 382.34MB / s. PCIe to FCU PCIe to RocketIO can be dynamically switched under the control of custom control information.
【學位授予單位】:浙江大學
【學位級別】:碩士
【學位授予年份】:2017
【分類號】:TN919.3
【參考文獻】
相關期刊論文 前3條
1 馬飛;劉琦;包斌;;基于FPGA的AXI4總線時序設計與實現(xiàn)[J];電子技術應用;2015年06期
2 林強;熊華鋼;張其善;;光纖通道綜述[J];計算機應用研究;2006年02期
3 黃永葵;光纖通道標準及其在航空電子中的應用[J];航空電子技術;2003年04期
,本文編號:2038874
本文鏈接:http://sikaile.net/kejilunwen/xinxigongchenglunwen/2038874.html