本文選題：JPEG2000 + DWT算法�。� 參考：《哈爾濱工業(yè)大學(xué)》2016年碩士論文

【摘要】：JPEG2000靜止圖像壓縮標(biāo)準(zhǔn)采用基于線性提升格式的DWT(Discrete Wavelet Transform)算法和EBCOT(Embedded Block Coding with Optimized Truncation)算法,因而擁有較JPEG標(biāo)準(zhǔn)更加優(yōu)越的性能。對于運(yùn)算密集的DWT算法和以比特位為編碼單位循環(huán)編碼的EBCOT算法,十分需要硬件加速與優(yōu)化。JPEG2000編碼和解碼部分擁有相似的優(yōu)化策略。針對DWT算法或IDWT算法,本文基于兩種一維小波變換核的變形格式,同時(shí)將設(shè)計(jì)的數(shù)據(jù)流圖映射為高度復(fù)用、關(guān)鍵路徑短且控制復(fù)雜度低的流水線硬件電路。EBCOT或EBDOT算法中,針對平面掃描算法,統(tǒng)一處理三個(gè)掃描通道減少硬件資源,并以條帶列為處理單位,條帶列和上下文狀態(tài)窗口生成流水處理,大幅減少處理周期;針對MQ算法,通過邏輯重組簡化關(guān)鍵處理路徑,在犧牲極少的存儲(chǔ)資源情況下預(yù)判重歸一化的左移次數(shù),大幅減少時(shí)鐘周期;針對Tier-2標(biāo)簽樹的硬件編解碼,設(shè)置行列奇偶屬性標(biāo)簽和父節(jié)點(diǎn)已編碼標(biāo)志行緩存便可實(shí)現(xiàn)任意分辨率圖像編解碼。編碼時(shí)需額外考慮碼率控制,遍歷比較得到已編碼碼塊的末位通道和當(dāng)前編碼的通道最小率失真值,選擇跳過當(dāng)前碼塊編碼,極大減少遍歷次數(shù)和冗余編碼過程,圖像失真略小于標(biāo)準(zhǔn)算法。基于上述硬件優(yōu)化方案,用Verilog HDL語言對硬件編解碼器進(jìn)行RTL級描述,采用基于“黃金模型”驗(yàn)證策略,自動(dòng)化比對關(guān)鍵驗(yàn)證點(diǎn)信息,完成功能仿真和時(shí)序仿真。之后搭建硬件SoC系統(tǒng),并以IP核掛載的方式嵌入硬件編解碼器,進(jìn)行系統(tǒng)仿真和軟件調(diào)試,完成FPGA驗(yàn)證。FPGA綜合結(jié)果表明,硬件編解碼器時(shí)鐘頻率均在170Mhz,硬件開銷較小,20倍壓縮比下能較好地平衡編解碼時(shí)間、圖像性能損失以及編解碼實(shí)時(shí)性等指標(biāo)。
[Abstract]:JPEG2000 still image compression standard adopts DWTG discrete Wavelet transform algorithm based on linear lifting scheme and EBCOT embedded Block coding with optimized algorithm, so it has better performance than JPEG standard. For the dense DWT algorithm and the EBCOT algorithm based on bits, it is very necessary for hardware acceleration and optimization. JPEG2000 coding and decoding have similar optimization strategy. For DWT algorithm or IDWT algorithm, based on two deformed schemes of one-dimensional wavelet transform kernel, the designed data flow diagram is mapped to pipeline hardware circuit. EBCOT or EBDOT algorithm, which has high multiplexing, short critical path and low control complexity. For plane scanning algorithm, three scanning channels are processed uniformly to reduce hardware resources, and pipeline processing is generated by strip column and context state window. The key processing path is simplified by logic recombination, and the number of renormalized left shifts is forecasted at the expense of very few storage resources, and the clock cycle is greatly reduced, and the hardware encoding and decoding for Tier-2 tag tree is also proposed. By setting the column parity attribute label and the parent node encoded flag line cache, the arbitrary resolution image encoding and decoding can be realized. When coding, the rate control should be taken into account, the traversal comparison can get the minimum rate-distortion value of the last channel of the coded block and the current coded channel, and skip the current block coding, greatly reduce the number of traversal and redundant coding process. Image distortion is slightly less than the standard algorithm. Based on the above hardware optimization scheme, the hardware codec is described at RTL level with Verilog HDL language, and the verification strategy based on "gold model" is adopted to automatically compare the information of key verification points, and complete the function simulation and timing simulation. Then the hardware SoC system is built, and the hardware codec is embedded in the IP core mount mode, and the system simulation and software debugging are carried out, and the FPGA verification. FPGA synthesis results show that, The clock frequency of the hardware codec is 170 MHz, and the hardware cost is less than 20 times compression ratio, which can balance the coding and decoding time, the loss of image performance and the real-time performance of the codec.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN919.81
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本文編號：2014658