本文選題：chirp信號(hào) + 鎖相環(huán)�。� 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：chirp信號(hào)又稱(chēng)啁啾信號(hào),因其發(fā)出的聲音類(lèi)似鳥(niǎo)叫聲”啁啾”而得名。作為一種典型的非平穩(wěn)信號(hào),在微波通信、聲吶、合成孔徑雷達(dá)成像等多個(gè)領(lǐng)域有廣泛的應(yīng)用。在雷達(dá)測(cè)量和電子對(duì)抗系統(tǒng)中chirp信號(hào)的帶寬、線(xiàn)性度、雜散度更是成為制約測(cè)量精度、對(duì)抗能力的最重要影響因素之一�？蒲蓄I(lǐng)域?qū)拵盘?hào)和非線(xiàn)性系統(tǒng)的需求日益增加的背景下,使寬帶、高線(xiàn)性度、低雜散度的chirp信號(hào)合成技術(shù)成為一項(xiàng)重要的研究課題。許多科研人員以及學(xué)者在chirp信號(hào)的高質(zhì)量合成方面進(jìn)行了大量的理論研究工作,提出了多種chirp信號(hào)合成的解決方案,并進(jìn)行了一定的實(shí)驗(yàn)及仿真,然而隨著科技水平的進(jìn)步,對(duì)高質(zhì)量chirp信號(hào)的要求越來(lái)越苛刻,主要包括帶寬、捷變、捕捉時(shí)間等等,已有的成果不能完全沒(méi)滿(mǎn)足科研的客觀(guān)需要,基礎(chǔ)制造業(yè)的發(fā)展,使更高頻率的芯片得以應(yīng)用,對(duì)已有的技術(shù)進(jìn)行創(chuàng)新,應(yīng)用新型的電子器件,能夠合成應(yīng)用于現(xiàn)階段科研項(xiàng)目需要的高質(zhì)量chirp信號(hào)。本文以chirp信號(hào)合成技術(shù)中實(shí)時(shí)帶寬、雜散度、以及相位噪聲的理論研究作為基礎(chǔ),著重分析了各環(huán)節(jié)的系統(tǒng)傳輸過(guò)程,給出了傳遞函數(shù)與關(guān)鍵指標(biāo)的制約關(guān)系,在此基礎(chǔ)上,建立了整個(gè)系統(tǒng)的數(shù)學(xué)模型。通過(guò)綜合論證幾種chirp信號(hào)合成的解決方案,提出了一種應(yīng)用高頻DDS芯片的寬帶快速入鎖鎖相環(huán)的chirp信號(hào)產(chǎn)生方法。針對(duì)S波段寬帶chirp信號(hào)存在的主要問(wèn)題,采用直接數(shù)字頻率合成技術(shù),鎖相環(huán)技術(shù),以及可編程邏輯器件進(jìn)行研究設(shè)計(jì)。完成了chirp信號(hào)合成環(huán)節(jié)中的大環(huán)路帶寬設(shè)計(jì)、低雜散度設(shè)計(jì)、寬帶VCO設(shè)計(jì)以及數(shù)字化設(shè)計(jì)的研究工作,制作了實(shí)際的產(chǎn)品,并對(duì)鎖相環(huán)鎖相時(shí)間,控制信號(hào)邏輯功能等系統(tǒng)設(shè)計(jì)關(guān)鍵環(huán)節(jié)進(jìn)行了仿真與試驗(yàn)檢測(cè)。仿真與實(shí)驗(yàn)結(jié)果證明,系統(tǒng)方案設(shè)計(jì)能夠滿(mǎn)足實(shí)際的科研工程需求,達(dá)到預(yù)期的設(shè)計(jì)指標(biāo)。chirp信號(hào)工作頻段2560MHz~2960MHz,帶寬可達(dá)到400MHz,鎖相時(shí)間小于10us;脈沖重復(fù)周期100us;單個(gè)脈沖占空比14/15;chirp信號(hào)的線(xiàn)性度小于10~(-4)。
[Abstract]:Chirp signal, also called chirp signal, is named after the chirp of bird call. As a typical nonstationary signal, it has been widely used in microwave communication, sonar, synthetic aperture radar imaging and other fields. In radar measurement and electronic countermeasure system, the bandwidth, linearity and spurious degree of chirp signal have become one of the most important factors that restrict the measurement accuracy and countermeasure capability. With the increasing demand for wideband signals and nonlinear systems in the field of scientific research, chirp signal synthesis technology with wide band, high linearity and low spurious degree has become an important research topic. Many researchers and scholars have done a lot of theoretical research on the high quality synthesis of chirp signal, put forward a variety of solutions of chirp signal synthesis, and carried out certain experiments and simulations. However, with the development of science and technology, The requirements for high quality chirp signals are becoming more and more stringent, including bandwidth, agility, capture time and so on. The existing achievements can not completely meet the objective needs of scientific research. The development of basic manufacturing industry has enabled higher frequency chips to be applied. By innovating the existing technology and applying new electronic devices, we can synthesize the high quality chirp signal which is needed in the current scientific research project. Based on the theoretical research of real-time bandwidth, spurious degree and phase noise in chirp signal synthesis technology, the system transmission process of each link is analyzed, and the restriction relation between transfer function and key index is given. The mathematical model of the whole system is established. By synthetically demonstrating several solutions of chirp signal synthesis, a method of chirp signal generation based on high frequency DDS chip is proposed. Aiming at the main problems of S-band wideband chirp signal, direct digital frequency synthesizer (DDS), phase-locked loop (PLL) and programmable logic device (PLD) are used to study and design. The design of large loop bandwidth, low spurious degree, wide band design and digital design of chirp signal synthesizer are completed. The actual product is made, and the phase locked time of PLL is analyzed. Control signal logic function and other key links of system design are simulated and tested. The simulation and experimental results show that the system scheme design can meet the actual needs of scientific research and engineering. The chirp signal has a bandwidth of 400 MHz, a phase locking time of less than 10us. a pulse repetition period of 100us. the linearity of a single pulse duty cycle of 14 / 15 chirp signal is less than 10mHz -4U.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TN957.51

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