本文選題：光纖通道 + 幀�。� 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：在短時(shí)間傳輸大量數(shù)據(jù)的需求越來越多時(shí),并行傳輸隨著工作頻率提高會遇到瓶頸。在高頻率遠(yuǎn)距離傳輸時(shí),即使并行的信號線長度上有細(xì)微的差別,在接收端相位也可能會有較大差別,同時(shí)也會有信號串?dāng)_問題。雖然一些措施可以解決這些問題,但代價(jià)通常很大。在高頻遠(yuǎn)距離傳輸時(shí),串行通信相比并行傳輸有不可比擬的優(yōu)勢。隨著半導(dǎo)體工藝水平的提高,串行器件的工作頻率可以做的很高,且不會有并行通信的串?dāng)_問題,使得單根信號線上的傳輸帶寬可以做到很大。相比普通的同軸電纜,光纖材質(zhì)作為傳輸介質(zhì)有很多優(yōu)點(diǎn)。依靠光在通路上來回反射傳輸,信號不易受電磁波干擾。傳輸帶寬可以很高,適合需要傳輸大量數(shù)據(jù)的場合。并且信號損耗低,遠(yuǎn)距離傳輸時(shí)不需要大量的信號中繼。本文對光纖通道的FC-FS協(xié)議進(jìn)行了詳細(xì)的分析,FC-FS協(xié)議說明了FC幀格式和光纖通道的基本控制特性。通過對光纖通道相關(guān)協(xié)議的分析,本文設(shè)計(jì)實(shí)現(xiàn)了光纖通道的傳輸物理層、編解碼層、幀傳輸層。物理層通過開發(fā)板自帶的RocketIO核和高速光電轉(zhuǎn)換模塊實(shí)現(xiàn)。幀編解碼層實(shí)現(xiàn)了發(fā)送端對32字節(jié)數(shù)據(jù)的編碼傳送和接收端數(shù)據(jù)對齊以及解碼還原。將幀數(shù)據(jù)和幀信息分別緩存,實(shí)現(xiàn)了發(fā)送端幀的組裝和接收端幀的提取機(jī)制。在接收端數(shù)據(jù)校驗(yàn)出錯時(shí),設(shè)計(jì)并仿真了一種差錯重傳的機(jī)制。實(shí)現(xiàn)了通路狀態(tài)控制器,為幀傳輸提供高速通道,并可處理傳送中常見異常。設(shè)計(jì)了緩存狀態(tài)控制器,在確保對方緩存空間足夠的情況下,可以向?qū)Ψ桨l(fā)送幀。通過以上模塊,設(shè)計(jì)實(shí)現(xiàn)了兩節(jié)點(diǎn)間幀的發(fā)送和提取。設(shè)計(jì)基于Xilinx Virtex 5平臺開發(fā),借助Isim等仿真工具對設(shè)計(jì)進(jìn)行了自底向上的仿真驗(yàn)證。通過nLint和Questa CDC等調(diào)試工具對設(shè)計(jì)中的波形仿真工具難以發(fā)現(xiàn)的潛在跨時(shí)鐘等問題進(jìn)行了查找與優(yōu)化,提高了系統(tǒng)的穩(wěn)定性。并通過Chipscope對設(shè)計(jì)進(jìn)行了板級調(diào)試,驗(yàn)證了設(shè)計(jì)的正確性。
[Abstract]:When the demand for a large amount of data is transmitted in a short time, the parallel transmission will meet the bottleneck with the increase of frequency. In the long distance transmission, even if there is a slight difference in the length of the parallel signal line, there may be a big difference at the receiver phase, and there will be a signal crosstalk problem. Some measures can be solved. With high frequency and long distance transmission, serial communication has an incomparable advantage over parallel transmission. With the improvement of semiconductor technology, the working frequency of serial devices can be very high, and there will be no parallel communication problem, which makes the transmission bandwidth of single signal line can be achieved very well. Compared with common coaxial cable, fiber material has many advantages as transmission medium. The signal is not easily interfered by electromagnetic wave depending on the transmission of light back and forth on the path. The transmission bandwidth can be very high, it is suitable for a large number of data, and the signal loss is low and the long distance transmission does not require a large number of signal relay. The FC-FS protocol of the fiber channel is analyzed in detail. The FC-FS protocol illustrates the basic control characteristics of the FC frame format and the fiber channel. Through the analysis of the fiber channel correlation protocol, the transmission physical layer, the codec layer, the frame transmission layer are designed and implemented. The physical layer is developed by developing the RocketIO core and the high-speed photoelectric conversion by the development board. The frame codec layer realizes the transmission and receiver data alignment and decoding reduction. The frame data and the frame information are cached separately. The transmission end frame assembly and the receiver frame extraction mechanism are realized. A error retransmission machine is designed and simulated when the data check is error at the receiver. The path state controller is implemented, which provides a high-speed channel for frame transmission and can handle the common exceptions in the transmission. A cache state controller is designed to send frames to each other to ensure that the other side's cache space is sufficient. Through the above modules, the frame is sent and extracted between the two nodes. The design is based on the Xilinx Virtex 5. The platform is developed with the aid of Isim and other simulation tools to verify the bottom up of the design. Through the debugging tools such as nLint and Questa CDC, the problems such as the potential cross clock, which are difficult to find by the waveform simulation tool in the design, are searched and optimized, and the stability of the system is improved. And the board level debugging is carried out through the Chipscope design. The correctness of the design is verified.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN929.11

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