A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel（FC）,Peripheral Component Interconnect Express（PCIe）,and RapidIO applications.To support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated（SST）transmitter（TX）,a passive receiver（RX）equalizer,a dual-loop phase locked loop（PLL）and a mixed signal clock and data recovery（CDR）unit.The proposed SST t... 

【文章來(lái)源】：Science China（Information Sciences）. 2014,57(06)EISCI

【文章頁(yè)數(shù)】：10 頁(yè)

【參考文獻(xiàn)】：
期刊論文
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