MICS接收機(jī)中小數(shù)分頻鎖相環(huán)的研究與設(shè)計
發(fā)布時間：2019-05-20 18:03
【摘要】：無線通訊市場的迅速增長,帶來了對高性能低成本射頻集成電路的迫切需求。同時半導(dǎo)體產(chǎn)業(yè)的迅猛發(fā)展也為所有通信模塊集成在一塊芯片上提供了可能。其中,最難集成的便是提供本振信號的鎖相環(huán)。因為鎖相環(huán)的相位噪聲很難滿足無線通信系統(tǒng)的相位噪聲需求。因此,對各種鎖相環(huán)的研究也越來越多。從整數(shù)分頻到小數(shù)分頻,從模擬到數(shù)字,鎖相環(huán)的性能不斷得到提升,而成本不斷降低。頻率合成器作為接收機(jī)中的關(guān)鍵模塊,其性能指標(biāo)直接決定了本振信號的精度和純度。由于整數(shù)分頻鎖相環(huán)的參考頻率為接收機(jī)信道寬度,且鎖相環(huán)的環(huán)路帶寬要求小于其參考頻率的十分之一。整數(shù)分頻鎖相環(huán)很難滿足MICS接收機(jī)快速鎖定,高分辨率的要求。因此,文中設(shè)計的頻率合成器采用了小數(shù)分頻鎖相環(huán)結(jié)構(gòu)。文中從基本的單元模塊到系統(tǒng)架構(gòu),對小數(shù)分頻鎖相環(huán)進(jìn)行了詳細(xì)的理論分析。并在理論分析的基礎(chǔ)上,設(shè)計了一個用于MICS無線收發(fā)系統(tǒng)的400MHz~430MHz的低功耗小數(shù)分頻電荷泵鎖相環(huán)。其中VCO采用四階差分結(jié)構(gòu)環(huán)形振蕩器,divider采用六位脈沖吞咽可編程分頻器,??調(diào)制器采用MASH1-1-1結(jié)構(gòu),電荷泵采用帶鏡像支路的電荷泵并用電壓跟隨器消除電荷共享,環(huán)路濾波器濾波器采用三階RC無源濾波器以抑制調(diào)制器高頻量化噪聲。文中首先根據(jù)MICS接收機(jī)系統(tǒng)指標(biāo)規(guī)劃了小數(shù)分頻鎖相環(huán)各模塊指標(biāo),并用MATLAB/Simulink建模驗證了指標(biāo)規(guī)劃的合理性。其次,在Cadence Spectre平臺下完成小數(shù)分頻鎖相環(huán)的設(shè)計仿真。再次,根據(jù)所設(shè)計的電路在Cadence Virtusoo下完成版圖設(shè)計,所設(shè)計的鎖相環(huán)芯片版圖總面積為0.8mm*1.2mm(含PAD)。后仿真時,小數(shù)分頻鎖相環(huán)的工作電壓為1.8V,輸出頻率范圍:400MHz~430MHz,信道寬度為300kHz,鎖定時間小于25us,小數(shù)雜散小于-50dBc,相位噪聲為-104dBc/Hz@1MHz。設(shè)計的鎖相環(huán),滿足MICS無線接收機(jī)的性能指標(biāo)要求。該小數(shù)分頻鎖相環(huán)芯片在GSMC0.18um工藝下流片,采用QFN24管腳封裝。測試時,VCO輸出頻率范圍為95MHz~741.7MHz,相位噪聲為-91.47dBc/Hz@1MHz。分頻器能正常工作,但整個鎖相環(huán)無法鎖定。后面對這次設(shè)計作了詳細(xì)的總結(jié),并提出了相應(yīng)的改進(jìn)措施。
[Abstract]:With the rapid growth of wireless communication market, there is an urgent demand for high performance and low cost RF integrated circuits. At the same time, the rapid development of semiconductor industry also provides the possibility for all communication modules to be integrated on one chip. Among them, the most difficult to integrate is to provide the local oscillator signal phase-locked loop. Because the phase noise of phase-locked loop is difficult to meet the phase noise requirements of wireless communication system. Therefore, there are more and more studies on all kinds of phase-locked loops. From integer frequency division to decimal frequency division, from analog to digital, the performance of phase-locked loop (PLL) is improved and the cost is reduced. As the key module of the receiver, the performance index of the frequency synthesizer directly determines the accuracy and purity of the local oscillator signal. Because the reference frequency of the integer frequency division phase-locked loop is the channel width of the receiver, and the loop bandwidth of the phase-locked loop is less than 1/10 of its reference frequency. Integer frequency division phase-locked loop is difficult to meet the requirements of fast locking and high resolution of MICS receiver. Therefore, the frequency synthesizer designed in this paper adopts the decimal frequency division phase-locked loop structure. In this paper, from the basic unit module to the system architecture, the decimal frequency division phase-locked loop is analyzed in detail. On the basis of theoretical analysis, a phase-locked loop of low power decimal charge pump for MICS wireless transceiver system is designed. Among them, VCO uses four-order differential ring oscillator, divider uses six-bit pulse swallowing programmable frequency divider, and divider adopts six-bit pulse swallowing programmable divider. The modulator adopts MASH1-1-1 structure, the charge pump adopts charge pump with mirror branch and the voltage follower is used to eliminate charge sharing. The loop filter adopts third-order RC passive filter to suppress the high frequency quantitative noise of modulator. In this paper, each module index of decimal frequency division phase-locked loop is planned according to the MICS receiver system index, and the rationality of the index planning is verified by MATLAB/Simulink modeling. Secondly, the design and simulation of phase-locked loop with decimal frequency division is completed on Cadence Spectre platform. Thirdly, according to the designed circuit, the layout design is completed under Cadence Virtusoo, and the total area of phase-locked loop chip layout is 0.8mm*1.2mm (including PAD). After simulation, the operating voltage of the phase-locked loop is 1.8 V, the output frequency range is 400MHz 鈮，
本文編號：2481845
[Abstract]:With the rapid growth of wireless communication market, there is an urgent demand for high performance and low cost RF integrated circuits. At the same time, the rapid development of semiconductor industry also provides the possibility for all communication modules to be integrated on one chip. Among them, the most difficult to integrate is to provide the local oscillator signal phase-locked loop. Because the phase noise of phase-locked loop is difficult to meet the phase noise requirements of wireless communication system. Therefore, there are more and more studies on all kinds of phase-locked loops. From integer frequency division to decimal frequency division, from analog to digital, the performance of phase-locked loop (PLL) is improved and the cost is reduced. As the key module of the receiver, the performance index of the frequency synthesizer directly determines the accuracy and purity of the local oscillator signal. Because the reference frequency of the integer frequency division phase-locked loop is the channel width of the receiver, and the loop bandwidth of the phase-locked loop is less than 1/10 of its reference frequency. Integer frequency division phase-locked loop is difficult to meet the requirements of fast locking and high resolution of MICS receiver. Therefore, the frequency synthesizer designed in this paper adopts the decimal frequency division phase-locked loop structure. In this paper, from the basic unit module to the system architecture, the decimal frequency division phase-locked loop is analyzed in detail. On the basis of theoretical analysis, a phase-locked loop of low power decimal charge pump for MICS wireless transceiver system is designed. Among them, VCO uses four-order differential ring oscillator, divider uses six-bit pulse swallowing programmable frequency divider, and divider adopts six-bit pulse swallowing programmable divider. The modulator adopts MASH1-1-1 structure, the charge pump adopts charge pump with mirror branch and the voltage follower is used to eliminate charge sharing. The loop filter adopts third-order RC passive filter to suppress the high frequency quantitative noise of modulator. In this paper, each module index of decimal frequency division phase-locked loop is planned according to the MICS receiver system index, and the rationality of the index planning is verified by MATLAB/Simulink modeling. Secondly, the design and simulation of phase-locked loop with decimal frequency division is completed on Cadence Spectre platform. Thirdly, according to the designed circuit, the layout design is completed under Cadence Virtusoo, and the total area of phase-locked loop chip layout is 0.8mm*1.2mm (including PAD). After simulation, the operating voltage of the phase-locked loop is 1.8 V, the output frequency range is 400MHz 鈮，
本文編號：2481845
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