基于FPGA的QPSK調(diào)制解調(diào)的設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2018-11-19 19:51
【摘要】：軟件無(wú)線電是當(dāng)今無(wú)線通信領(lǐng)域的一項(xiàng)具有前沿性的技術(shù),它的基本思想是從模塊化、標(biāo)準(zhǔn)化和通用化的角度出發(fā),追求無(wú)線通信系統(tǒng)的全頻段、多模式、和可重構(gòu)的操作方式。在符合軟件無(wú)線電的通信系統(tǒng)中,用戶能夠根據(jù)自己的需求定義該硬件平臺(tái)的各種各樣的基本功能。從而使硬件電路的設(shè)計(jì)如同軟件設(shè)計(jì)一樣方便,也得軟件無(wú)線電廣泛的應(yīng)用于通信領(lǐng)域的各方面。QPSK調(diào)制方式是數(shù)字調(diào)制方式的一種,因其頻帶利用率高,抗干擾能力強(qiáng),傳輸速率快等特點(diǎn)廣泛應(yīng)用于現(xiàn)代數(shù)字通信系統(tǒng)中�，F(xiàn)場(chǎng)可編程門陣列(Field Programmable Array,FPGA)用于數(shù)字電路設(shè)計(jì)時(shí),用硬件電路描述語(yǔ)言進(jìn)行數(shù)字電路設(shè)計(jì),具有開(kāi)發(fā)過(guò)程投資小、開(kāi)發(fā)周期短、開(kāi)發(fā)智能化和可重構(gòu)等特點(diǎn)。由此可見(jiàn),用FPGA來(lái)實(shí)現(xiàn)QPSK調(diào)制解調(diào)符合軟件無(wú)線電的思想,所以用FPGA來(lái)實(shí)現(xiàn)QPSK調(diào)制解調(diào)具有重要的意義。本文首先給出了基于FPGA的QPSK調(diào)制解調(diào)設(shè)計(jì)與實(shí)現(xiàn)的背景與意義,即在軟件無(wú)線電的思想背景下用FPGA設(shè)計(jì)QPSK調(diào)制解調(diào)系統(tǒng)。分析了QPSK調(diào)制解調(diào)技術(shù)的研究現(xiàn)狀、FPGA的發(fā)展和用FPGA來(lái)實(shí)現(xiàn)QPSK調(diào)制解調(diào)的實(shí)際意義。對(duì)QPSK調(diào)制解調(diào)的原理與系統(tǒng)設(shè)計(jì)框圖進(jìn)行了詳細(xì)的說(shuō)明,為文中具體電路的設(shè)計(jì)提供了堅(jiān)實(shí)的理論基礎(chǔ)。調(diào)制端由向上混頻器、成型濾波器、數(shù)控振蕩器和加法器組成,本文重點(diǎn)對(duì)成型濾波器和數(shù)控振蕩器進(jìn)行了設(shè)計(jì)和實(shí)現(xiàn),通過(guò)采用升余弦滾降濾波器來(lái)對(duì)基帶信號(hào)進(jìn)行濾波成型處理,解決了基帶信號(hào)頻帶寬和碼間串?dāng)_的問(wèn)題;通過(guò)查表法來(lái)產(chǎn)生兩路正交的正弦信號(hào),解決了因載波正交性不好而導(dǎo)致的QPSK星座圖歧變問(wèn)題。解調(diào)電路由向下混頻器、匹配濾波器、載波同步模塊、位同步模塊和取樣判決模塊等組成。本文重點(diǎn)對(duì)載波同步模塊和位同步模塊進(jìn)行了設(shè)計(jì)和實(shí)現(xiàn),載波同步采用Costas鎖相環(huán)來(lái)實(shí)現(xiàn),位同步采用Gardner鎖相環(huán)來(lái)實(shí)現(xiàn)。Costas環(huán)中的鑒相器,本文對(duì)傳統(tǒng)的乘法器作為鑒相器做了一定的改進(jìn),改用差分鑒相器來(lái)實(shí)現(xiàn),從而一定程度上提高了鑒相器的靈敏度,又通過(guò)用環(huán)路濾波器的輸出來(lái)控制環(huán)路中的數(shù)控振蕩器的頻率控制字,來(lái)實(shí)現(xiàn)環(huán)路的穩(wěn)定性和準(zhǔn)確輸出,因此Costas鎖相環(huán)來(lái)實(shí)現(xiàn)載波同步提高了解調(diào)端載波恢復(fù)的準(zhǔn)確度。Gardner鎖相環(huán)中的插值濾波器,本文對(duì)傳統(tǒng)的濾波器結(jié)構(gòu)做了一定的改進(jìn)而采用并行工作的立方內(nèi)插濾波器,提高了數(shù)據(jù)處理速度;而Gardner鎖相環(huán)本身的特性獨(dú)立于載波同步的特性,所以提高了位同步的性能。在MATLAB建模仿真驗(yàn)證各個(gè)設(shè)計(jì)的正確性的基礎(chǔ)上,借助Quartus II平臺(tái),用硬件電路描述語(yǔ)言Verilog來(lái)實(shí)現(xiàn)了QPSK調(diào)制解調(diào)系統(tǒng)中的各個(gè)設(shè)計(jì)模塊,并將最后將產(chǎn)生的下載的文件下載到Altera公司的Cyclone II系列的EP2C35F672C6NX芯片上完成了QPSK調(diào)制解調(diào)的FPGA實(shí)現(xiàn)。在這過(guò)程中還用Modelsim對(duì)編譯后的Verilog文件進(jìn)行功能仿真,分析設(shè)計(jì)中各個(gè)模塊的仿真波形,驗(yàn)證Verilog程序設(shè)計(jì)的正確性。最后通過(guò)對(duì)解調(diào)出的信號(hào)和調(diào)制端發(fā)射的信號(hào),在示波器是進(jìn)行顯示對(duì)比,驗(yàn)證了論文中QPSK調(diào)制解調(diào)電路設(shè)計(jì)和實(shí)現(xiàn)的正確性。本文在分析了QPSK調(diào)制解調(diào)技術(shù)原理的基礎(chǔ)上,對(duì)調(diào)制端和解調(diào)端的各個(gè)模塊包括成型濾波器、數(shù)控振蕩器、載波同步、位同步等模塊進(jìn)行了詳細(xì)的MATLAB建模仿真分析和FPGA實(shí)現(xiàn),實(shí)現(xiàn)了發(fā)送信號(hào)經(jīng)發(fā)送端QPSK調(diào)制發(fā)射后,經(jīng)接收端解調(diào)后得到了正確的發(fā)送數(shù)據(jù),達(dá)到了預(yù)期的效果。本課題是借助之前實(shí)習(xí)公司的項(xiàng)目完成,由于篇幅和工作量的原因,本課題只涉及其中的調(diào)制解調(diào)部分。
[Abstract]:Software radio is a front-edge technology in the field of wireless communication, and its basic idea is to pursue the full-band, multi-mode and reconfigurable operation of the wireless communication system from the perspective of modularization, standardization and generalization. In a software radio-compliant communication system, a user is able to define a wide variety of basic functions of the hardware platform in accordance with their needs. so that the design of the hardware circuit is as convenient as the software design, and the software radio is widely applied to all aspects of the communication field. The QPSK modulation scheme is a kind of digital modulation method, which is widely used in modern digital communication system because of its high frequency band utilization rate, strong anti-interference ability and high transmission rate. The field programmable gate array (FPGA) is used in the digital circuit design. The hardware circuit description language is used to design the digital circuit. The field programmable gate array (FPGA) has the characteristics of small development process investment, short development cycle, intelligent and reconfigurable development. It can be seen that the implementation of QPSK modulation and demodulation with FPGA is in accordance with the idea of software radio, so it is of great significance to implement QPSK modulation and demodulation with FPGA. This paper first gives the background and significance of the design and implementation of QPSK modulation and demodulation based on FPGA, that is, the QPSK modulation and demodulation system is designed with FPGA in the background of software radio. The research status of QPSK modulation and demodulation technology, the development of FPGA and the practical significance of QPSK modulation and demodulation are analyzed. The principle and system design block diagram of QPSK modulation and demodulation are described in detail, which provides a solid theoretical basis for the design of the circuit. the modulation end is composed of an upward mixer, a shaping filter, a numerical control oscillator and an adder, the problem of the band width of the baseband signal and the crosstalk of the codes is solved, two orthogonal sine signals are generated by a look-up table method, and the problem of the QPSK constellation problem caused by the bad carrier orthogonality is solved. The demodulation circuit is composed of a down mixer, a matched filter, a carrier synchronization module, a bit synchronization module and a sampling decision module. In this paper, the carrier synchronization module and the bit synchronization module are designed and implemented. The carrier synchronization is realized by a Costas phase-locked loop, and the bit synchronization is realized by a Gardner phase-locked loop. The phase detector in the Costas loop is modified by the traditional multiplier as the phase detector, and the differential phase detector is used to realize the phase detector, so that the sensitivity of the phase detector is improved to a certain extent, and the frequency control word of the numerical control oscillator in the loop is controlled by the output of the loop filter, so as to realize the stability and the accurate output of the loop, so the Costas phase-locked loop can realize the carrier synchronization and improve the accuracy of the carrier recovery of the modulation end. The interpolation filter in the Gardner phase-locked loop has improved the performance of bit synchronization by making a certain improvement on the traditional filter structure and adopting a parallel-working cubic interpolation filter to improve the data processing speed; and the characteristic of the Gardner phase-locked loop itself is independent of the carrier-synchronous characteristic, so the bit-synchronization performance is improved. On the basis of MATLAB modeling and simulation to verify the correctness of each design, using the Quartus II platform, the hardware circuit description language Verilog is used to implement the various design modules in the QPSK modulation and demodulation system. and the finally generated downloaded file is downloaded to the EP2C35F672C6NX chip of the Cyclin II series of Altera, and the FPGA implementation of the QPSK modulation and demodulation is completed. In this process, the compiled Verilog file is simulated by Modelsim, and the simulation waveform of each module in the design is analyzed, and the correctness of Verilog programming is verified. and finally, the signal transmitted by the demodulated signal and the modulation end is compared, and the correctness of the circuit design and the implementation of the QPSK modulation and demodulation circuit in the paper is verified. In this paper, based on the analysis of the principle of QPSK modulation and demodulation, the modules including the shaping filter, the numerical control oscillator, the carrier synchronization, the bit synchronization and the like of the modulation end and the demodulation terminal are described in detail with the MATLAB modeling and simulation analysis and the FPGA implementation. and after the transmission signal is modulated and transmitted through the transmission end QPSK, the correct transmission data is obtained after being demodulated by the receiving end, and the expected effect is achieved. The subject is completed by the project of the former practice company, and the subject only relates to the modulation and demodulation part of the subject due to the length and the workload.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791;TN915.05
本文編號(hào)：2343263
[Abstract]:Software radio is a front-edge technology in the field of wireless communication, and its basic idea is to pursue the full-band, multi-mode and reconfigurable operation of the wireless communication system from the perspective of modularization, standardization and generalization. In a software radio-compliant communication system, a user is able to define a wide variety of basic functions of the hardware platform in accordance with their needs. so that the design of the hardware circuit is as convenient as the software design, and the software radio is widely applied to all aspects of the communication field. The QPSK modulation scheme is a kind of digital modulation method, which is widely used in modern digital communication system because of its high frequency band utilization rate, strong anti-interference ability and high transmission rate. The field programmable gate array (FPGA) is used in the digital circuit design. The hardware circuit description language is used to design the digital circuit. The field programmable gate array (FPGA) has the characteristics of small development process investment, short development cycle, intelligent and reconfigurable development. It can be seen that the implementation of QPSK modulation and demodulation with FPGA is in accordance with the idea of software radio, so it is of great significance to implement QPSK modulation and demodulation with FPGA. This paper first gives the background and significance of the design and implementation of QPSK modulation and demodulation based on FPGA, that is, the QPSK modulation and demodulation system is designed with FPGA in the background of software radio. The research status of QPSK modulation and demodulation technology, the development of FPGA and the practical significance of QPSK modulation and demodulation are analyzed. The principle and system design block diagram of QPSK modulation and demodulation are described in detail, which provides a solid theoretical basis for the design of the circuit. the modulation end is composed of an upward mixer, a shaping filter, a numerical control oscillator and an adder, the problem of the band width of the baseband signal and the crosstalk of the codes is solved, two orthogonal sine signals are generated by a look-up table method, and the problem of the QPSK constellation problem caused by the bad carrier orthogonality is solved. The demodulation circuit is composed of a down mixer, a matched filter, a carrier synchronization module, a bit synchronization module and a sampling decision module. In this paper, the carrier synchronization module and the bit synchronization module are designed and implemented. The carrier synchronization is realized by a Costas phase-locked loop, and the bit synchronization is realized by a Gardner phase-locked loop. The phase detector in the Costas loop is modified by the traditional multiplier as the phase detector, and the differential phase detector is used to realize the phase detector, so that the sensitivity of the phase detector is improved to a certain extent, and the frequency control word of the numerical control oscillator in the loop is controlled by the output of the loop filter, so as to realize the stability and the accurate output of the loop, so the Costas phase-locked loop can realize the carrier synchronization and improve the accuracy of the carrier recovery of the modulation end. The interpolation filter in the Gardner phase-locked loop has improved the performance of bit synchronization by making a certain improvement on the traditional filter structure and adopting a parallel-working cubic interpolation filter to improve the data processing speed; and the characteristic of the Gardner phase-locked loop itself is independent of the carrier-synchronous characteristic, so the bit-synchronization performance is improved. On the basis of MATLAB modeling and simulation to verify the correctness of each design, using the Quartus II platform, the hardware circuit description language Verilog is used to implement the various design modules in the QPSK modulation and demodulation system. and the finally generated downloaded file is downloaded to the EP2C35F672C6NX chip of the Cyclin II series of Altera, and the FPGA implementation of the QPSK modulation and demodulation is completed. In this process, the compiled Verilog file is simulated by Modelsim, and the simulation waveform of each module in the design is analyzed, and the correctness of Verilog programming is verified. and finally, the signal transmitted by the demodulated signal and the modulation end is compared, and the correctness of the circuit design and the implementation of the QPSK modulation and demodulation circuit in the paper is verified. In this paper, based on the analysis of the principle of QPSK modulation and demodulation, the modules including the shaping filter, the numerical control oscillator, the carrier synchronization, the bit synchronization and the like of the modulation end and the demodulation terminal are described in detail with the MATLAB modeling and simulation analysis and the FPGA implementation. and after the transmission signal is modulated and transmitted through the transmission end QPSK, the correct transmission data is obtained after being demodulated by the receiving end, and the expected effect is achieved. The subject is completed by the project of the former practice company, and the subject only relates to the modulation and demodulation part of the subject due to the length and the workload.
【學(xué)位授予單位】：成都理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791;TN915.05
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 隋德良;QPSK中頻全數(shù)字解調(diào)器的設(shè)計(jì)與FPGA實(shí)現(xiàn)[D];南京理工大學(xué);2010年
，本文編號(hào)：2343263
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