【摘要】：隨著毫米波技術(shù)的迅猛發(fā)展以及電子系統(tǒng)的不斷更新?lián)Q代,其對毫米波頻率源的性能要求越來越嚴格。倍頻鏈路是實現(xiàn)毫米波頻率源的一種重要方式,它不僅能降低系統(tǒng)的振蕩頻率,同時兼具微波波段高的頻率穩(wěn)定度和低的相位噪聲等優(yōu)點。本文以倍頻鏈路為基礎(chǔ),采用微波鎖相環(huán)+倍頻鏈路的方式實現(xiàn)了104GHz倍頻源。倍頻源的相位噪聲性能取決于基波信號源,這是本文的難點之一。本文首先對鎖相環(huán)的基本結(jié)構(gòu)、傳遞函數(shù)及其噪聲模型進行理論分析。在此基礎(chǔ)上,采用鎖相式頻率技術(shù),設計了具有低相噪、低雜散的13GHz基波信號源。測試結(jié)果顯示13GHz鎖相環(huán)的相位噪聲達到-109.89dBc/Hz@10kHz;在2GHz帶寬范圍內(nèi),雜散抑制度優(yōu)于-70dBc。倍頻鏈路中末級二倍頻器的倍頻效率直接決定了倍頻源的輸出功率,準確的二極管模型以及采用變?nèi)莨苁翘岣弑额l效率的關(guān)鍵所在。本文根據(jù)MA46H146變?nèi)莨艿腃-V曲線提取其關(guān)鍵物理參數(shù),并根據(jù)器件尺寸及經(jīng)典的物理公式,使用三維電磁仿真軟件HFSS建立三維封裝模型。在此基礎(chǔ)之上,使用HFSS和ADS相結(jié)合的方法,設計了串聯(lián)單管結(jié)構(gòu)的F波段二倍頻器。測試結(jié)果表明,當輸入驅(qū)動功率為80mW,外加-5V偏置電壓時,二倍頻器在103GHz處的輸出功率達到12.6mW,倍頻效率達到15%。在104GHz處的輸出功率為7.7mW。目前,在此頻段,國內(nèi)還未見使用單管二倍頻器獲得相似的倍頻效率。而且,二倍頻器的仿真曲線和實測曲線一致性較好。最后,本文對104GHz本振源模塊進行了整體性能測試。測試結(jié)果表明:104GHz源模塊輸出功率為8.6mW;相位噪聲為-90.55dBc/Hz@10kHz;在3GHz帶寬范圍內(nèi),雜散抑制度優(yōu)于-60dBc。
[Abstract]:With the rapid development of millimeter wave technology and the updating of electronic system, the performance requirements of millimeter wave frequency source are becoming more and more strict. Frequency doubling link is an important way to realize millimeter wave frequency source. It can not only reduce the oscillation frequency of the system, but also have the advantages of high frequency stability and low phase noise in microwave band. In this paper, based on the frequency doubling link, the microwave phase locked loop frequency doubling link is used to realize the 104GHz frequency doubling source. The phase noise performance of the frequency multiplier depends on the fundamental signal source, which is one of the difficulties in this paper. In this paper, the basic structure, transfer function and noise model of PLL are analyzed theoretically. Based on this, a 13GHz fundamental signal source with low phase noise and low spurious noise is designed by using phase-locked frequency technology. The results show that the phase noise of 13GHz PLL is -109.89dBc / Hz-10kHz, and the spurious suppression is better than -70dBc. within the bandwidth of 2GHz. The frequency doubling efficiency of the last stage frequency multiplier in the frequency doubling link directly determines the output power of the frequency doubling source. Accurate diode model and the use of varactor are the key to improve the frequency doubling efficiency. In this paper, the key physical parameters of MA46H146 varactor are extracted according to its C-V curve. According to the size of the device and the classical physical formula, the three-dimensional packaging model is established by using the three-dimensional electromagnetic simulation software HFSS. On this basis, using the method of combining HFSS and ADS, the F band frequency multiplier with series single transistor structure is designed. The test results show that when the input driving power is 80mW and the bias voltage is -5V, the output power of the doubler at 103GHz reaches 12.6mW, and the frequency doubling efficiency reaches 15mW. The output power at 104GHz is 7.7 MW. At present, no similar frequency doubling efficiency has been achieved in this frequency band by using a single-transistor doubler. Moreover, the simulation curve of the doubler is in good agreement with the measured curve. Finally, the overall performance of the 104GHz local oscillator module is tested. The test results show that the output power of the: 104GHz source module is 8.6 MW, the phase noise is -90.55dBc / Hzr @ 10kHz, and the spurious suppression is better than -60dBc. in the 3GHz bandwidth.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN851.4

【參考文獻】

相關(guān)碩士學位論文 前1條

1 詹銘周;W波段鎖相倍頻源技術(shù)研究[D];電子科技大學;2007年

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本文編號：2256383