去隔行算法的FPGA實(shí)現(xiàn)
發(fā)布時間：2018-09-14 15:35
【摘要】：隨著高清數(shù)字電視(HDTV)的推廣,人們對視頻質(zhì)量的要求也在逐漸變高。傳統(tǒng)的PAL制視頻由于分辨率過低,在數(shù)字視頻上顯示讓人觀感不舒服。同時由隔行掃描帶來的畫面模糊,運(yùn)動鋸齒現(xiàn)象,讓畫面顯得更加難看,這就會影響在工程實(shí)踐中實(shí)際顯示的美感。而且在工程實(shí)踐中,傳統(tǒng)用DSP來實(shí)現(xiàn)去隔行的處理,不僅操作繁瑣而且也顯得太浪費(fèi)資源。所以運(yùn)用FPGA來實(shí)現(xiàn)視頻圖像的去隔行便應(yīng)運(yùn)而生。本文在開始介紹了FPGA的有關(guān)知識,接著便對不同類型的去隔行算法進(jìn)行了較詳細(xì)的說明,在對它們進(jìn)行了比較和分析后,進(jìn)行了一定改進(jìn),給出了一種適合在FPGA上實(shí)現(xiàn)的算法,并針對提出的算法,在FPGA上進(jìn)行了具體的實(shí)現(xiàn)。本文的算法是首先運(yùn)用前后四場的數(shù)據(jù)進(jìn)行第一次運(yùn)動檢測,在此同時也進(jìn)行相應(yīng)的場內(nèi)插操作。然后通過場內(nèi)插數(shù)據(jù)來進(jìn)行第二次運(yùn)動檢測,最終將像素點(diǎn)區(qū)分為靜止點(diǎn)和運(yùn)動點(diǎn),并通過選用不同的值,最終獲得去隔行的結(jié)果。對該算法進(jìn)行資源實(shí)現(xiàn)評估后,將算法劃分為具體模塊。研究了DDR2 SDRAM芯片的相關(guān)操作及其控制器IP核的使用。用VHDL語言對模塊進(jìn)行實(shí)現(xiàn)后,下載到FPGA板卡上運(yùn)行,并在顯示器上進(jìn)行了實(shí)時顯示。通過觀察去隔行的圖像,得知該方法能較好的消除模糊、鋸齒等不良現(xiàn)象,證明了FPGA方案實(shí)現(xiàn)的可靠性,優(yōu)越性。
[Abstract]:With the promotion of high definition digital TV (HDTV), the requirement of video quality is becoming higher and higher. Traditional PAL video is uncomfortable to display on digital video because of its low resolution. At the same time, the picture blurred by interlacing scan, the phenomenon of motion sawtooth makes the picture look more ugly, which will affect the aesthetic sense of actual display in engineering practice. In engineering practice, the traditional use of DSP to realize the interlacing processing is not only cumbersome operation but also a waste of resources. Therefore, the use of FPGA to achieve video image de-interlacing came into being. This paper introduces the knowledge of FPGA at the beginning, then explains the different kinds of de-interlacing algorithms in detail. After comparing and analyzing them, it improves them, and gives an algorithm that is suitable to be implemented on FPGA. The algorithm is implemented on FPGA. The algorithm of this paper firstly uses the data of four fields to detect the first motion, and carries on the corresponding field interpolation operation at the same time. Then the second motion detection is carried out through the field interpolation data. Finally, the pixels are divided into static points and moving points. Finally, the results of de-interlacing are obtained by selecting different values. After evaluating the resource of the algorithm, the algorithm is divided into specific modules. The related operation of DDR2 SDRAM chip and the use of IP core are studied. After the module is implemented in VHDL language, it is downloaded to the FPGA board to run and displayed in real time on the monitor. By observing the interlaced images, we can see that this method can eliminate the bad phenomena such as blur and sawtooth, and prove the reliability and superiority of the FPGA scheme.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN941
本文編號：2243127
[Abstract]:With the promotion of high definition digital TV (HDTV), the requirement of video quality is becoming higher and higher. Traditional PAL video is uncomfortable to display on digital video because of its low resolution. At the same time, the picture blurred by interlacing scan, the phenomenon of motion sawtooth makes the picture look more ugly, which will affect the aesthetic sense of actual display in engineering practice. In engineering practice, the traditional use of DSP to realize the interlacing processing is not only cumbersome operation but also a waste of resources. Therefore, the use of FPGA to achieve video image de-interlacing came into being. This paper introduces the knowledge of FPGA at the beginning, then explains the different kinds of de-interlacing algorithms in detail. After comparing and analyzing them, it improves them, and gives an algorithm that is suitable to be implemented on FPGA. The algorithm is implemented on FPGA. The algorithm of this paper firstly uses the data of four fields to detect the first motion, and carries on the corresponding field interpolation operation at the same time. Then the second motion detection is carried out through the field interpolation data. Finally, the pixels are divided into static points and moving points. Finally, the results of de-interlacing are obtained by selecting different values. After evaluating the resource of the algorithm, the algorithm is divided into specific modules. The related operation of DDR2 SDRAM chip and the use of IP core are studied. After the module is implemented in VHDL language, it is downloaded to the FPGA board to run and displayed in real time on the monitor. By observing the interlaced images, we can see that this method can eliminate the bad phenomena such as blur and sawtooth, and prove the reliability and superiority of the FPGA scheme.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN941
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中國博士學(xué)位論文全文數(shù)據(jù)庫 前1條
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中國碩士學(xué)位論文全文數(shù)據(jù)庫 前1條
1 李旭;基于運(yùn)動補(bǔ)償?shù)娜ジ粜邢到y(tǒng)的研究與FPGA設(shè)計(jì)[D];大連理工大學(xué);2005年
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