發(fā)布時(shí)間：2018-08-27 09:06

【摘要】：HSUPA(高速上行分組接入)技術(shù)是WCDMA系統(tǒng)中上行鏈路的演進(jìn)技術(shù)，該技術(shù)通過(guò)采用更容易實(shí)現(xiàn)的E-DCH復(fù)合編解碼傳輸、可選的更短的時(shí)間間隔(TTI)、HARQ重傳機(jī)制等關(guān)鍵技術(shù)，，可大幅度提高WCDMA系統(tǒng)的上行數(shù)據(jù)傳輸速率。 本論文首先介紹WCDMAHSUPA的技術(shù)特點(diǎn)和發(fā)展?fàn)顩r，闡述了HSUPA的專(zhuān)有結(jié)構(gòu)和特性，對(duì)HSUPA關(guān)鍵技術(shù)如Node B控制的調(diào)度、HARQ、更短的TTI進(jìn)行了描述。 隨后，為實(shí)現(xiàn)更大的上行數(shù)據(jù)傳輸吞吐率，著重分析了HSUPA技術(shù)中MAC-es協(xié)議層在FPGA上的實(shí)現(xiàn)過(guò)程，以Verilog語(yǔ)言為基礎(chǔ)對(duì)系統(tǒng)進(jìn)行了設(shè)計(jì)及實(shí)現(xiàn)，包括MAC-es協(xié)議層系統(tǒng)的架構(gòu)、基于FPGA的系統(tǒng)各子層的實(shí)現(xiàn)方案，其中重點(diǎn)介紹了HSUPA數(shù)據(jù)包重排序問(wèn)題的處理方法和MAC-es層數(shù)據(jù)包PDU的解析與分流。 最后編寫(xiě)了測(cè)試用例，搭建了系統(tǒng)仿真測(cè)試平臺(tái)，使用ModelSim軟件對(duì)設(shè)計(jì)方案進(jìn)行了單元功能及系統(tǒng)級(jí)功能仿真與測(cè)試。仿真結(jié)果表明，本論文提出的方案能夠?qū)崿F(xiàn)設(shè)計(jì)目標(biāo)，是切實(shí)可行的。
[Abstract]:HSUPA (High Speed uplink packet access) technology is the evolution technology of uplink in WCDMA system. This technology adopts the more easily realized E-DCH composite codec transmission, the optional shorter time interval (TTI) / HARQ retransmission mechanism and so on. The uplink data transmission rate of WCDMA system can be greatly improved. This paper first introduces the technical characteristics and development of WCDMAHSUPA, expounds the proprietary structure and characteristics of HSUPA, and describes the key technologies of HSUPA, such as Node B control scheduling and shorter TTI. Then, in order to realize more uplink data transmission throughput, the implementation process of MAC-es protocol layer on FPGA in HSUPA technology is analyzed emphatically. The system is designed and implemented based on Verilog language, including the architecture of MAC-es protocol layer system. The implementation scheme of each sub-layer of the system based on FPGA is introduced, in which the processing method of the HSUPA packet reordering problem and the parsing and shunting of the MAC-es layer packet PDU are introduced. Finally, the test cases are written, the system simulation and test platform is built, and the unit function and system-level function simulation and test are carried out with ModelSim software. The simulation results show that the proposed scheme can achieve the design goal and is feasible.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN929.5

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1 朱元林;HSUPA中MAC-es協(xié)議的FPGA硬件設(shè)計(jì)[D];華中科技大學(xué);2014年

本文編號(hào)：2206775