HEVC標(biāo)準(zhǔn)中整數(shù)變換的FPGA實(shí)現(xiàn)
發(fā)布時(shí)間：2018-08-27 08:09
【摘要】：新一代視頻編碼標(biāo)準(zhǔn)(High Efficiency Video Coding,HEVC)中整數(shù)DCT編碼支持大小從4×4到32×32的TU塊,運(yùn)算量巨大。通過優(yōu)化MCM單元來減少運(yùn)算量,通過硬件電路復(fù)用來減少硬件資源消耗,同時(shí)使用轉(zhuǎn)置模塊來加速流水線,并且能適應(yīng)各種不同大小的TU塊。實(shí)驗(yàn)代碼通過Verilog HDL編寫,并在Altera Arria GX EP1AGX90EF1152C FPGA上綜合。結(jié)果表明,該結(jié)構(gòu)等待時(shí)延最多為32個(gè)時(shí)鐘周期,每個(gè)時(shí)鐘周期能處理32個(gè)采樣點(diǎn),在184 MHz的時(shí)鐘頻率下,能實(shí)時(shí)處理60 f/s(幀/秒)的UHD(Ultra-High-Definition 7 680×4 320)視頻信號(hào)。
[Abstract]:In the next generation of video coding standard (High Efficiency Video Coding,HEVC), integer DCT coding supports TU blocks ranging from 4 脳 4 to 32 脳 32. The MCM unit is optimized to reduce the computation cost, the hardware circuit reuse is used to reduce the hardware resource consumption, and the transpose module is used to speed up the pipeline, and it can adapt to various TU blocks of different sizes. The experimental code is written by Verilog HDL and synthesized on Altera Arria GX EP1AGX90EF1152C FPGA. The results show that the time delay of the structure is up to 32 clock cycles, and each clock cycle can process 32 sampling points. At the clock frequency of 184 MHz, the UHD (Ultra-High-Definition 7 680 脳 4 320) video signal of 60 f / s (frame / second) can be processed in real time.
【作者單位】： 福州大學(xué)工業(yè)控制研究所;
【分類號(hào)】：TN919.81
[Abstract]:In the next generation of video coding standard (High Efficiency Video Coding,HEVC), integer DCT coding supports TU blocks ranging from 4 脳 4 to 32 脳 32. The MCM unit is optimized to reduce the computation cost, the hardware circuit reuse is used to reduce the hardware resource consumption, and the transpose module is used to speed up the pipeline, and it can adapt to various TU blocks of different sizes. The experimental code is written by Verilog HDL and synthesized on Altera Arria GX EP1AGX90EF1152C FPGA. The results show that the time delay of the structure is up to 32 clock cycles, and each clock cycle can process 32 sampling points. At the clock frequency of 184 MHz, the UHD (Ultra-High-Definition 7 680 脳 4 320) video signal of 60 f / s (frame / second) can be processed in real time.
【作者單位】： 福州大學(xué)工業(yè)控制研究所;
【分類號(hào)】：TN919.81
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