【摘要】：由于Camera Link視頻信號具有高分辨率、高傳輸速度、圖像處理靈活、通信協(xié)議簡單、傳輸接口結構易于實現(xiàn)等優(yōu)勢,因此近年來在民用領域如安防監(jiān)控、視覺遙感、多媒體處理等方面具有大量的市場需求。本論文以FPGA為核心處理器,研制了一套能夠采集并處理Camera Link視頻信號,并支持多種視頻接口顯示的處理系統(tǒng)。 本文首先對系統(tǒng)的功能需求進行了分析,在此基礎上提出以FPGA為核心器件的Camera Link視頻信號處理系統(tǒng)的設計方案。方案中系統(tǒng)采集Camera Link相機的圖像數(shù)據(jù),將數(shù)據(jù)的色彩空間由Bayer轉換為RGB或YUV,處理后的數(shù)據(jù)存儲到SDRAM中,并分別用ADV7343和ADV7123視頻編碼芯片完成復合視頻接口輸出和VGA接口輸出。接著設計硬件電路的原理圖和PCB板,并對系統(tǒng)硬件電路平臺進行了搭建與調試。然后重點研究了Camera Link相機功能模式,通過串口通信完成對相機工作方式的配置,并對視頻信號的處理進行了初步探討。最后編寫視頻處理系統(tǒng)軟件,對CameraLink視頻信號進行采集、處理并存儲,用FPGA普通I/O口模擬IIC總線對視頻編碼芯片進行配置,將視頻信號以多種格式輸出顯示。
[Abstract]:Because Camera Link video signal has the advantages of high resolution, high transmission speed, flexible image processing, simple communication protocol and easy implementation of transmission interface, it has been widely used in the field of civil security monitoring and visual remote sensing in recent years. Multimedia processing and other aspects have a lot of market demand. In this paper, FPGA is used as the core processor to develop a processing system which can collect and process Camera Link video signals and support multiple video interfaces. Based on the analysis of the functional requirements of the system, a design scheme of Camera Link video signal processing system based on FPGA is proposed in this paper. In the scheme, the image data of Camera Link camera is collected, and the color space of the data is converted from Bayer to RGB or YUV, and stored in SDRAM. The composite video interface output and VGA interface output are completed by ADV7343 and ADV7123 video coding chip respectively. Then the schematic diagram and PCB board of the hardware circuit are designed, and the hardware circuit platform of the system is built and debugged. Then the function mode of Camera Link camera is studied emphatically, the configuration of camera working mode is accomplished by serial port communication, and the processing of video signal is discussed preliminarily. Finally, the software of video processing system is written, the CameraLink video signal is collected, processed and stored, and the video coding chip is configured with FPGA I / O port analog IIC bus, and the video signal is output and displayed in various formats.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN911.7

【參考文獻】

相關期刊論文 前1條

1 王經典;楊愛良;;一種BT.656到XGA視頻格式轉換結構的FPGA實現(xiàn)[J];航空電子技術;2010年03期

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本文編號：2204019