【摘要】：軟件無線電技術(shù)在無線通信領(lǐng)域應(yīng)用廣泛，是近幾年的熱點(diǎn)研究話題。本文結(jié)合實(shí)驗(yàn)室承擔(dān)的國(guó)家十二五規(guī)劃項(xiàng)目“液體安全性無損檢測(cè)”和關(guān)于雷達(dá)信號(hào)處理的國(guó)防項(xiàng)目，研究了軟件無線電技術(shù)中的一些關(guān)鍵技術(shù)，討論了危險(xiǎn)液體無損檢測(cè)系統(tǒng)中數(shù)字下變頻關(guān)鍵技術(shù)、數(shù)字基帶信號(hào)的瞬時(shí)相位提取以及國(guó)防科技項(xiàng)目中關(guān)于雷達(dá)信號(hào)雜波圖處理等問題。 射頻接收的模擬信號(hào)經(jīng)過A/D采樣之后的信號(hào)具有較高的頻率，不便于數(shù)據(jù)處理，而數(shù)字下變頻技術(shù)能夠?qū)⒏咚俑哳l率的信號(hào)進(jìn)行降頻和抽取，獲得較低的采樣速率，有助于后續(xù)的基帶數(shù)據(jù)處理。本研究重點(diǎn)討論了數(shù)字下變頻技術(shù)的優(yōu)化，運(yùn)用數(shù)控振蕩器和乘法器實(shí)現(xiàn)混頻技術(shù)，并運(yùn)用CIC濾波器實(shí)現(xiàn)抽取，，省去了后續(xù)半帶濾波器和FIR濾波器模塊，并利用ModelSim和MATLAB對(duì)設(shè)計(jì)進(jìn)行仿真和數(shù)據(jù)分析。并在ALTERA公司的EP2S90F1090I4上進(jìn)行驗(yàn)證試驗(yàn)，試驗(yàn)表明本文中所采用的優(yōu)化的方法是可行的，不僅能提高運(yùn)算效率，而且大大節(jié)約硬件資源。 基帶數(shù)據(jù)處理涉及到數(shù)據(jù)處理算法和系統(tǒng)資源、速度等的優(yōu)化，也是近幾年軟件無線電技術(shù)的熱點(diǎn)。結(jié)合危險(xiǎn)液體無損檢測(cè)系統(tǒng)，研究了對(duì)基帶信號(hào)的瞬時(shí)相位的提取，重點(diǎn)講述了運(yùn)用CORDIC算法求取瞬時(shí)相位，并對(duì)誤差較大的盲點(diǎn)進(jìn)行修正。運(yùn)用MATLAB對(duì)算法進(jìn)行理論分析，然后仿硬件的處理方式進(jìn)行設(shè)計(jì)實(shí)現(xiàn)，仿真分析數(shù)據(jù)運(yùn)算誤差并進(jìn)行修正，然后進(jìn)行代碼設(shè)計(jì)和FPGA實(shí)現(xiàn)，并運(yùn)用signaltap抓取數(shù)據(jù)，分析數(shù)據(jù)誤差，實(shí)驗(yàn)選用ALTERA公司的cyclone IV系列FPGA設(shè)計(jì)，實(shí)驗(yàn)證明數(shù)據(jù)誤差均在0.5度要求的范圍之內(nèi)，并且時(shí)鐘頻率在150Mhz以上，隨后進(jìn)行系統(tǒng)的優(yōu)化，節(jié)約資源并且將時(shí)鐘頻率提高到200Mhz以上，性能較好，達(dá)到設(shè)計(jì)要求。 國(guó)防項(xiàng)目中雷達(dá)雜波圖信號(hào)處理系統(tǒng)重點(diǎn)研究了雜波圖處理系統(tǒng)的各個(gè)模塊的FPGA實(shí)現(xiàn)，根據(jù)項(xiàng)目要求，重點(diǎn)講述了數(shù)據(jù)乒乓緩存、數(shù)據(jù)包扇區(qū)更新時(shí)的雜波圖迭代運(yùn)算，扇區(qū)不更新時(shí)對(duì)同扇區(qū)數(shù)據(jù)選大或平均處理以及背景數(shù)據(jù)的擴(kuò)展回傳等問題。并在xilinx公司的virtex-II pro上進(jìn)行FPGA驗(yàn)證，分析了實(shí)驗(yàn)結(jié)果，表明設(shè)計(jì)正確。
[Abstract]:Software radio technology is widely used in the field of wireless communication, which is a hot topic in recent years. In this paper, some key technologies in software radio technology are studied in combination with the national non-destructive testing of liquid safety and the national defense project on radar signal processing, which is the 12th Five-Year Plan Project undertaken by the laboratory. This paper discusses the key techniques of digital downconversion in the NDT system of dangerous liquids, the instantaneous phase extraction of digital baseband signals, and the clutter map processing of radar signals in the national defense science and technology project. The analog signals received by RF have a high frequency and are not easy to process data because of the high frequency after Ar / D sampling. The digital downconversion technology can decimate and decimate the signals of high speed and high frequency to obtain a lower sampling rate. Facilitate subsequent baseband data processing. This study focuses on the optimization of digital down-conversion technology, the use of numerical control oscillator and multiplier to achieve mixing technology, and the use of CIC filter to achieve decimation, eliminating the follow-up half-band filter and FIR filter module, The design is simulated and analyzed by ModelSim and MATLAB. The experimental results on EP2S90F1090I4 of ALTERA Company show that the optimization method is feasible and can not only improve the efficiency of operation, but also save the hardware resources greatly. Baseband data processing involves the optimization of data processing algorithms, system resources, speed and so on. It is also a hot topic in software radio technology in recent years. Combined with the dangerous liquid nondestructive testing system, the extraction of instantaneous phase of baseband signal is studied. The CORDIC algorithm is used to calculate the instantaneous phase, and the blind spot with big error is corrected. The algorithm is analyzed theoretically by MATLAB, then designed and implemented by the processing mode of imitation hardware, the error of data operation is analyzed and corrected by simulation, then the code design and FPGA implementation are carried out, and the data error is analyzed by using signaltap to capture data. The design of cyclone IV series FPGA made by ALTERA Company is used in the experiment. The experiment proves that the error of data is within the range of 0.5 degree and the clock frequency is above 150Mhz. Then the system is optimized, the resource is saved and the clock frequency is raised above 200Mhz. Good performance, meet the design requirements. In the national defense project, the radar clutter map signal processing system focuses on the FPGA implementation of each module of the clutter map processing system. According to the requirements of the project, the paper focuses on the iterative operation of the clutter map when the data ping-pong cache and the data packet sector are updated. When the sector is not updated, the data of the same sector is selected or processed in average and the background data is extended back. FPGA verification is carried out on the virtex-II pro of xilinx Company, and the experimental results show that the design is correct.
【學(xué)位授予單位】：煙臺(tái)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN92

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