發(fā)布時(shí)間：2018-06-24 05:10

  本文選題：視頻壓縮 + FPGA��； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：近年來(lái),視頻圖像采集及傳輸?shù)膽?yīng)用遍布于人類社會(huì)的各個(gè)領(lǐng)域。因而,視頻壓縮技術(shù)也受到越來(lái)越多學(xué)者的關(guān)注。為了更好地進(jìn)行視頻壓縮,視頻壓縮標(biāo)準(zhǔn)應(yīng)運(yùn)而生。當(dāng)前應(yīng)用較廣也較成熟的壓縮標(biāo)準(zhǔn)為H.264。H.264與之前發(fā)布的標(biāo)準(zhǔn)相比,壓縮性能上有較大提高,使用也更加靈活,應(yīng)用范圍也更廣。H.264標(biāo)準(zhǔn)可以根據(jù)不同的應(yīng)用場(chǎng)景提供不同的檔次和相應(yīng)的編碼工具包。在壓縮性能提升的同時(shí),壓縮標(biāo)準(zhǔn)也變得更加復(fù)雜。因此實(shí)現(xiàn)編碼標(biāo)準(zhǔn)需要先進(jìn)的硬件及軟件的支持。本文在綜合考慮后,選用當(dāng)下應(yīng)用較廣且較實(shí)用的FPGA+DSP混合架構(gòu)來(lái)實(shí)現(xiàn)視頻壓縮及可靠傳輸系統(tǒng),并對(duì)其進(jìn)行了深入研究,主要的研究成果為:1.對(duì)視頻壓縮算法進(jìn)行研究。首先對(duì)視頻壓縮標(biāo)準(zhǔn)發(fā)展歷史及現(xiàn)狀進(jìn)行了介紹;接著介紹了視頻壓縮的基本知識(shí),指出在目前傳輸技術(shù)和存儲(chǔ)條件下進(jìn)行視頻壓縮是必要的,同時(shí)指出視頻可以被壓縮,是通過(guò)去除視頻圖像中的時(shí)間上和空間上及人眼視覺(jué)上的冗余來(lái)實(shí)現(xiàn)的;之后重點(diǎn)介紹了H.264視頻壓縮標(biāo)準(zhǔn)的詳細(xì)框架及使用的關(guān)鍵技術(shù):幀間預(yù)測(cè)、幀內(nèi)預(yù)測(cè)、去塊濾波器、變換和量化、熵編碼及碼率控制等。2.對(duì)FPGA+DSP的混合架構(gòu)進(jìn)行了研究。首先對(duì)應(yīng)用FPGA進(jìn)行系統(tǒng)開(kāi)發(fā)的優(yōu)勢(shì)及FPGA的器件選型做了研究;接著研究了DSP處理器的特點(diǎn)及DSP器件的選型;最后經(jīng)過(guò)綜合考慮選擇了基于FPGA+DSP的混合視頻架構(gòu)進(jìn)行視頻壓縮傳輸系統(tǒng)的實(shí)現(xiàn),并確定了FPGA和DSP的選型及各自在視頻壓縮傳輸系統(tǒng)中的分工。3.對(duì)混合架構(gòu)的視頻壓縮傳輸系統(tǒng)的可用方案進(jìn)行研究。首先對(duì)視頻圖像可用的預(yù)處理方案做了研究,包括針對(duì)進(jìn)入視頻壓縮傳輸系統(tǒng)的視頻格式的預(yù)處理方案,針對(duì)視頻圖像中的亮度和色度信號(hào)的可選預(yù)處理方案,及針對(duì)視頻圖像的緩存機(jī)制可選的方案;接著對(duì)FPGA與DSP間協(xié)同處理時(shí)用到的接口及協(xié)議做了研究,包括原始視頻的傳輸、壓縮碼流的傳輸以及DSP與FPGA的協(xié)同啟動(dòng);之后對(duì)壓縮后碼流的可靠傳輸方案進(jìn)行了研究;最后對(duì)解碼端系統(tǒng)及可選顯示方案進(jìn)行了研究。4.對(duì)混合架構(gòu)的視頻壓縮傳輸系統(tǒng)進(jìn)行了實(shí)現(xiàn)。首先設(shè)計(jì)出了一個(gè)針對(duì)特定需求的編碼端的方案實(shí)現(xiàn)框圖,詳細(xì)說(shuō)明整個(gè)流程及各個(gè)模塊的功能;最后給出相應(yīng)的解碼端方案實(shí)現(xiàn)框圖、處理流程及內(nèi)部設(shè)定的部分具體參數(shù),同時(shí)給出部分modelsim仿真圖。
[Abstract]:In recent years, video image acquisition and transmission are widely used in various fields of human society. As a result, video compression technology has attracted more and more attention of scholars. In order to better carry out video compression, video compression standard came into being. The compression standard H.264.H.264, which is widely used and mature, has better compression performance and is more flexible in use than the standard published before. The H.264 standard can provide different grades and corresponding coding toolkits according to different application scenarios. As compression performance improves, compression standards become more complex. Therefore, the implementation of coding standards needs the support of advanced hardware and software. In this paper, we choose the widely used and practical FPGA DSP hybrid architecture to realize the video compression and reliable transmission system, and do a deep research on it. The main research results are as follows: 1. The video compression algorithm is studied. This paper first introduces the history and present situation of video compression standard, then introduces the basic knowledge of video compression, points out that it is necessary to compress video under the current transmission technology and storage conditions, and points out that video can be compressed. It is realized by removing the redundancy of time, space and human vision in video image, and then introduces the detailed frame of H.264 video compression standard and the key technologies used: interframe prediction, intra prediction, deblocking filter, etc. Transform and quantization, Entropy coding and rate control, etc. The hybrid architecture of FPGA DSP is studied. Firstly, the advantages of using FPGA to develop the system and the device selection of FPGA are studied, then the characteristics of DSP processor and the selection of DSP device are studied. Finally, the hybrid video architecture based on FPGA DSP is selected to implement the video compression transmission system, and the selection of FPGA and DSP and the division of labor between FPGA and DSP are determined. The available scheme of video compression transmission system based on hybrid architecture is studied. Firstly, the available preprocessing schemes for video images are studied, including the preprocessing schemes for the video format entering the video compression transmission system, and the optional preprocessing schemes for the brightness and chrominance signals in the video images. Then, the interface and protocol used in collaborative processing between FPGA and DSP are studied, including the transmission of original video, the transmission of compressed bitstream and the cooperative startup between DSP and FPGA. After that, the reliable transmission scheme of compressed bitstream is studied. Finally, the decoding system and optional display scheme are studied. A hybrid video compression transmission system is implemented. First of all, a scheme implementation block diagram is designed to meet the specific requirements, and the whole flow and the functions of each module are explained in detail. Finally, the corresponding decoding implementation block diagram, processing flow and some specific parameters set inside are given. At the same time, part of the modelsim simulation diagram is given.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.81

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相關(guān)期刊論文 前1條

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本文編號(hào)：2060168