本文選題：SDF + FFT處理器��； 參考：《北京理工大學(xué)》2014年博士論文

【摘要】：我們生活在一個(gè)技術(shù)日新月異的時(shí)代。這主要是歸功于數(shù)字系統(tǒng)逐漸緩慢地取代舊的模擬系統(tǒng)并快速的發(fā)展進(jìn)步。如今，，數(shù)字系統(tǒng)正面對(duì)最苛刻的信號(hào)處理應(yīng)用方面的要求，包含了強(qiáng)約束條件下如時(shí)鐘頻率，吞吐量，功耗，延遲和實(shí)時(shí)計(jì)算方面的要求。為了滿足這些強(qiáng)約束條件下的要求，通常需要求助于硬件設(shè)備諸如ASIC（特定用途集成電路）或FPGA（現(xiàn)場(chǎng)可編程門陣列），因此這些設(shè)備需要在信號(hào)處理算法的計(jì)算方面達(dá)到一個(gè)非常高的性能。 然而，設(shè)計(jì)硬件電路并不是一件簡單的事。首先硬件方面不同于傳統(tǒng)的數(shù)學(xué)，例如：一個(gè)算法的數(shù)學(xué)簡化并不一定會(huì)導(dǎo)致一個(gè)更簡單的電路。其次任何算法存在許多不同的硬件實(shí)現(xiàn)。從實(shí)現(xiàn)算法的計(jì)算所使用每一個(gè)存儲(chǔ)器和一個(gè)處理器，到直接執(zhí)行完成整個(gè)的算法的硬件電路都是不唯一的，即把每個(gè)乘法轉(zhuǎn)換成一個(gè)乘法器，把每個(gè)加法轉(zhuǎn)換成一個(gè)加法器。第三在硬件編程時(shí)，效率始終是一個(gè)隱含的要求。信號(hào)處理的諸多要求，如時(shí)鐘頻率，延遲或吞吐量必須加以考慮。 用于計(jì)算一個(gè)特定的算法的電路形式主要取決于所需的性能。直接實(shí)現(xiàn)流圖可能會(huì)獲得具有高吞吐量的電路，但其面積和功耗會(huì)非常高。含有存儲(chǔ)器和運(yùn)算單元的系統(tǒng)會(huì)占用更少面積，但它將具有高延遲和低吞吐量。因此，流水線結(jié)構(gòu)往往是首選，因?yàn)樗鼈兲峁┝烁叩男盘?hào)處理能力以及相當(dāng)?shù)偷挠布�，此外，效率不僅包括某種架構(gòu)的選擇，而且所選擇的類型是理想的設(shè)計(jì)。硬件實(shí)現(xiàn)是希望用于最大限度地提高性能或降低功耗的應(yīng)用程序，因此該架構(gòu)必須為了實(shí)現(xiàn)這些目標(biāo)，進(jìn)行優(yōu)化。 本論文研究了FFT架構(gòu)在FPGA上最優(yōu)的實(shí)現(xiàn)。SDF架構(gòu)被認(rèn)為是一種最優(yōu)實(shí)現(xiàn)，因?yàn)樗鼭M足大多數(shù)通信體系結(jié)構(gòu)的要求。需要特別注意的是如何使設(shè)計(jì)結(jié)果有效地映射到目標(biāo)FPGA的粗粒度的硬件結(jié)構(gòu)，可以得到更好的實(shí)施結(jié)果。通過針對(duì)Virtex-4和Virtex-6器件映射R2的SDF架構(gòu)的FFT處理器進(jìn)行了說明。這種設(shè)計(jì)FPGA的映射已被詳細(xì)探討和研究�？墒潜疚奶岢隽艘粋�(gè)更好的映射的轉(zhuǎn)換算法，從而實(shí)現(xiàn)的效果，遠(yuǎn)遠(yuǎn)超越了先前發(fā)表的作品。 除此之外，以22次方為基底的不同等價(jià)算法進(jìn)行了仿真，他們具有相同的實(shí)現(xiàn)復(fù)雜度但是在隨后的旋轉(zhuǎn)因子系數(shù)間可能有著較少的轉(zhuǎn)換。對(duì)進(jìn)一步的轉(zhuǎn)子的交替進(jìn)行了對(duì)比，以觀察對(duì)于特定的旋轉(zhuǎn)角度哪種方式有著最少的加法次數(shù)。
[Abstract]:We live in an era of rapid technological change. This is largely due to the slow replacement of the old analog system by the digital system and its rapid development. Today, digital systems are facing the most demanding requirements for signal processing applications, including the requirements of strong constraints such as clock frequency, throughput, power consumption, delay and real-time computing. In order to meet the requirements under these strong constraints, Hardware devices such as ASIC (Special purpose Integrated Circuits) or FPGA (Field Programmable Gate Array) are often required to achieve a very high performance in the computation of signal processing algorithms. However, the design of hardware circuits is not a simple matter. First, hardware is different from traditional mathematics. For example, mathematical simplification of an algorithm does not necessarily lead to a simpler circuit. Secondly, there are many different hardware implementations for any algorithm. From every memory and one processor used to implement the calculation of the algorithm, the hardware circuit that directly executes the whole algorithm is not unique, that is, each multiplication is converted into a multiplier, and each addition is converted into an adder. Third, in hardware programming, efficiency is always an implicit requirement. Many requirements for signal processing, such as clock frequency, delay, or throughput, must be considered. The circuit form used to calculate a particular algorithm depends mainly on the desired performance. Direct implementation of flow diagrams may result in high throughput circuits, but their area and power consumption will be very high. Systems with memory and computing units will consume less space, but will have high latency and low throughput. Therefore, pipelined structures are often preferred because they provide high signal processing capabilities and relatively low hardware requirements. In addition, efficiency includes not only the choice of some architecture, but also the type chosen is the ideal design. Hardware implementation is an application that is intended to maximize performance or reduce power consumption, so the architecture must be optimized to achieve these goals. In this paper, the optimal implementation of FFT architecture on FPGA. SDF architecture is considered as an optimal implementation because it meets the requirements of most communication architectures. Special attention should be paid to how to effectively map the design results to the coarse-grained hardware structure of the target FPGA and obtain better implementation results. The FFT processor of SDF architecture which maps R2 to Virtex-4 and Virtex-6 devices is introduced. The mapping of this design FPGA has been discussed and studied in detail. However, a better mapping algorithm is proposed, which is far more effective than previous works. In addition, different equivalent algorithms based on the 22 th power are simulated. They have the same implementation complexity but may have less conversion between the subsequent rotation factor coefficients. Further rotors are compared to see which method has the least number of additions for a particular rotation angle.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.7

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