本文選題：可重構(gòu)接收機 + 射頻采樣��； 參考：《電子科技大學》2014年碩士論文

【摘要】：隨著現(xiàn)代電子通信集成技術(shù)的飛速發(fā)展,可重構(gòu)雷達數(shù)字接收機已成為國內(nèi)外學者研究的熱點�？芍貥�(gòu)直接射頻采樣數(shù)字接收機能夠在不做硬件變動的前提下通過調(diào)整自身參數(shù)來實現(xiàn)不同頻段、帶寬信號的接收。這樣不僅硬件體積得到大大減小,同時還可以根據(jù)接收信號的不同進行實時調(diào)整,具有很強的靈活性和可擴展性。本文針對可重構(gòu)直接射頻采樣接收機的結(jié)構(gòu)進行了分析,從工作原理和理論推導等方面出發(fā)介紹了可重構(gòu)直接射頻采樣接收機與傳統(tǒng)接收機的不同之處。然后提出一種可重構(gòu)射頻采樣接收機的實施方案,通過Matlab對系統(tǒng)做仿真分析并結(jié)合FPGA實現(xiàn)驗證接收機結(jié)構(gòu)的合理性以及可實現(xiàn)性。本文研究的主要內(nèi)容包括:1、針對可重構(gòu)直接射頻采樣接收機的結(jié)構(gòu)進行理論分析與介紹,包括可重構(gòu)接收機的工作原理以及實現(xiàn)中所涉及到的相關(guān)理論基礎(chǔ);2、圍繞可重構(gòu)射頻采樣接收機結(jié)構(gòu)中的關(guān)鍵技術(shù)進行研究,推導了射頻脈沖采樣過程中脈沖串的脈寬以及采樣時鐘的抖動對接收信號的影響,并結(jié)合Matlab仿真,驗證了時鐘源的不穩(wěn)定對系統(tǒng)信噪比的影響;3、從射頻采樣時鐘抖動引起系統(tǒng)信噪比的變化出發(fā),建立了去抖動噪聲模型。將去噪過程分兩個步驟,首先從模擬端引入校準信號,通過校準信號的相位變化反推射頻信號的抖動相位從而對抖動噪聲進行抑制,其次研究基帶信號的去噪算法從而進一步提高接收機的信噪比;4、提出一種基于雙波段信號接收的可重構(gòu)接收機設(shè)計方案,對ADC采樣后的信號作數(shù)字混頻下變頻以及CIC級聯(lián)濾波器、HB級聯(lián)濾波器進行抽取濾波和自適應濾波等過程進行了Matlab仿真,驗證了方案的合理性;5、將設(shè)計方案在FPGA中加以實現(xiàn),并將Modelsim和Matlab綜合起來仿真結(jié)果證明方案的可行性。
[Abstract]:With the rapid development of modern electronic communication integration technology, the reconfigurable radar digital receiver has become a hot research topic of scholars at home and abroad. The reconfigurable direct radio frequency sampling digital receiver can realize the reception of different frequency band and bandwidth signal by adjusting its own parameters without changing the hardware. In this way, not only the hardware volume is greatly reduced, but also the received signal can be adjusted in real time, which is flexible and extensible. In this paper, the structure of the reconfigurable direct radio frequency sampling receiver is analyzed, and the differences between the reconfigurable direct radio frequency sampling receiver and the traditional receiver are introduced from the aspects of working principle and theoretical derivation. Then a scheme of reconfigurable RF sampling receiver is proposed. The system is simulated and analyzed by Matlab and the rationality and realizability of the receiver structure are verified by FPGA. The main contents of this paper include: 1. The structure of the reconfigurable direct radio frequency sampling receiver is analyzed and introduced theoretically. Including the working principle of the reconfigurable receiver and the related theoretical foundation involved in the implementation, the key technologies in the structure of the reconfigurable RF sampling receiver are studied. The influence of pulse width of the pulse string and the jitter of the sampling clock on the received signal in the process of RF pulse sampling is deduced, and combined with Matlab simulation, The influence of clock source instability on system SNR is verified. Based on the variation of SNR caused by RF sampling clock jitter, a de-jitter noise model is established. The de-noising process is divided into two steps: first, the calibration signal is introduced from the analog end, and the jitter phase of the RF signal is pushed back by the phase change of the calibration signal to suppress the jitter noise. Secondly, the de-noising algorithm of baseband signal is studied to further improve the signal-to-noise ratio (SNR) of receiver. A design scheme of reconfigurable receiver based on dual-band signal reception is proposed. The process of decimation filter and adaptive filter are simulated by Matlab. The rationality of the scheme is verified by Matlab simulation, and the design scheme is implemented in FPGA. The simulation results of Modelsim and Matlab show the feasibility of the scheme.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN957.5

【參考文獻】

中國碩士學位論文全文數(shù)據(jù)庫 前1條

1 白光宇;射頻可重構(gòu)濾波器設(shè)計[D];北京交通大學;2010年

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本文編號：2013521