發(fā)布時(shí)間：2018-06-02 23:11

  本文選題：沖激雷達(dá) + 窄脈沖�。� 參考：《電子科技大學(xué)》2014年碩士論文

【摘要】：超寬帶沖激雷達(dá)是一種通過(guò)發(fā)射極窄的脈沖信號(hào)進(jìn)行目標(biāo)探測(cè)、定位和成像的新型雷達(dá),它具有良好的穿透性能、極高的距離分辨率和超低的功耗等優(yōu)點(diǎn)。可以應(yīng)用于地質(zhì)探測(cè)、室內(nèi)定位,反隱身技術(shù)、穿墻反恐、叢林探測(cè)、生命救援、機(jī)場(chǎng)安監(jiān)系統(tǒng)等各種民用和軍事領(lǐng)域。本文圍繞超寬帶沖激雷達(dá)收發(fā)系統(tǒng)的關(guān)鍵技術(shù),主要開(kāi)展了以下幾個(gè)方面的工作:(1)介紹了超寬帶沖激雷達(dá)的歷史、發(fā)展現(xiàn)狀、技術(shù)優(yōu)勢(shì)和研究意義。闡述了超寬帶沖激雷達(dá)的基本理論,包括沖激雷達(dá)系雷達(dá)方程和沖激雷達(dá)發(fā)射機(jī)接收機(jī)的關(guān)鍵技術(shù)理論等。(2)分別基于雪崩三極管和階躍恢復(fù)二極管理論,設(shè)計(jì)并制作了兩款超寬帶窄脈沖源。從原理上分析了影響脈沖幅度、寬度的各個(gè)因素。制作的雪崩脈沖源最大幅度為3V,最小脈寬約為1ns,階躍脈沖源最小脈寬為350ps,幅度最大為950mV。結(jié)果表明雪崩技術(shù)可以得到更大幅度的脈沖,而階躍技術(shù)得到的脈沖信號(hào)脈寬更小。(3)基于放大器的負(fù)反饋理論,通過(guò)在低噪放晶體管的源極上添加電容以彌補(bǔ)高頻增益。利用ADS軟件快速優(yōu)化輸入輸出端口的匹配阻抗,同時(shí)選擇合適的反饋電阻,和附加優(yōu)化目標(biāo),使端口阻抗達(dá)到優(yōu)化目標(biāo)要求的值。避免了在斯密斯圓圖上尋找最佳匹配點(diǎn)的繁瑣步驟�；诖�,仿真并制作了帶寬在0.1~1GHz,增益為38dB,輸入輸出端口S參數(shù)小于-10及噪聲系數(shù)低于2的超寬帶放大器。(4)在等效采樣理論的基礎(chǔ)上,通過(guò)FPGA產(chǎn)生10個(gè)頻率為200MHz的時(shí)鐘信號(hào),該時(shí)鐘信號(hào)經(jīng)過(guò)低抖動(dòng)延時(shí)芯片CDCF5801延時(shí)52ps(等效采樣率20GS/S)后送給模數(shù)轉(zhuǎn)換器MAX1121作為采樣時(shí)鐘。經(jīng)過(guò)192次延時(shí)采樣,一個(gè)完整的回波信號(hào)被采集到FPGA內(nèi)部的緩存FIFO中,采集的數(shù)據(jù)經(jīng)過(guò)BLOCKRAM的數(shù)據(jù)重組,得到正確的波形數(shù)據(jù)順序,最后由FPGA控制固態(tài)存儲(chǔ)器AT45DB161D把數(shù)據(jù)燒寫(xiě)到其內(nèi)部的存儲(chǔ)單元中,需要后端信號(hào)處理和分析時(shí),再由FPGA讀出并經(jīng)過(guò)串口MAX232傳輸?shù)絇C機(jī)。該電路以較低的成本在以FR-4為基板的四層板上實(shí)現(xiàn)了超寬帶沖激雷達(dá)的數(shù)據(jù)采集,避免了昂貴的高速ADC的購(gòu)買。兼顧系統(tǒng)性能的同時(shí)很好的控制了成本。
[Abstract]:Ultra-wideband impulse radar is a new type of radar for target detection, location and imaging through very narrow pulse signals. It has the advantages of good penetration, high range resolution and ultra-low power consumption. Can be used in geological exploration, indoor positioning, anti-stealth technology, anti-wall anti-terrorist, jungle exploration, life rescue, airport safety monitoring system and other civil and military fields. Focusing on the key technology of UWB impulse radar transceiver system, this paper mainly introduces the history, development status, technical advantages and research significance of UWB impulse radar in the following aspects: 1. The basic theory of ultra-wideband impulse radar, including the radar equation of impulse radar system and the key technology theory of receiver of impulse radar transmitter, etc., based on the theory of avalanche transistor and step recovery diode, respectively. Two UWB narrow pulse sources are designed and fabricated. The influence factors of pulse amplitude and width are analyzed in principle. The maximum amplitude of avalanche pulse source is 3V, the minimum pulse width is about 1ns, the minimum pulse width of step pulse source is 350psand the maximum amplitude is 950mV. The results show that the avalanche technique can obtain a larger pulse, while the pulse width obtained by the step technique is smaller. Based on the negative feedback theory of the amplifier, the capacitor is added to the source pole of the low noise amplifier transistor to compensate for the high frequency gain. The matching impedance of the input and output ports is quickly optimized by using ADS software. At the same time, the appropriate feedback resistor is selected, and the additional optimization target is added to make the port impedance reach the value required by the optimization goal. The complicated steps of finding the best matching point on the Smith circle are avoided. Based on this, an UWB amplifier with a bandwidth of 0.1 GHz, a gain of 38 dB, an input and output port S parameter of less than -10 and a noise coefficient of less than 2 is simulated and fabricated. On the basis of equivalent sampling theory, 10 clock signals with 200MHz frequency are generated by FPGA. The clock signal is sent to the A / D converter MAX1121 as the sampling clock after the delay of 52 pss (equivalent sampling rate 20 GS / S) of the low jitter delay chip CDCF5801. After 192 time delay sampling, a complete echo signal was collected into the buffer FIFO of FPGA, and the collected data was reorganized by BLOCKRAM to obtain the correct waveform data order. Finally, the solid state memory (AT45DB161D) is controlled by FPGA to burn the data into its internal memory cell. When the back-end signal is processed and analyzed, the data is read out by FPGA and transmitted to PC through serial port MAX232. The circuit realizes the data acquisition of UWB impulse radar on a four-layer board based on FR-4 at lower cost, thus avoiding the purchase of expensive high-speed ADC. At the same time, the system performance is well controlled.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN958

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本文編號(hào)：1970549