本文選題：PLL測試 + 抖動因素　； 參考：《國防科學(xué)技術(shù)大學(xué)》2014年碩士論文

【摘要】：鎖相環(huán)(PLL)作為時鐘芯片廣泛應(yīng)用于無線通信、消費(fèi)電子等現(xiàn)代IC產(chǎn)品中,其功能包括相位同步和時鐘倍頻等。衡量PLL性能優(yōu)劣的關(guān)鍵指標(biāo)之一為抖動(在頻域表現(xiàn)為相位噪聲)特性,在PLL芯片測試中,如何精確衡量PLL的時鐘抖動特性已成為日漸重要的課題。針對PLL的抖動評估,在設(shè)計階段的電路模擬遠(yuǎn)遠(yuǎn)不夠,只有對流片后的成品芯片進(jìn)行功能驗(yàn)證和可靠性測試,才能最終斷言設(shè)計是否正確。本文將詳細(xì)闡述PLL芯片的測試原理與抖動因素探究,具體工作如下:(1)闡述PLL的工作原理、噪聲分析及電路級抖動模擬。(2)搭建PLL測試平臺,分析抖動參數(shù)的物理意義,應(yīng)用示波器、相噪儀、測試板、數(shù)據(jù)分析軟件等設(shè)備對實(shí)體芯片進(jìn)行各項指標(biāo)測量,以驗(yàn)證PLL的性能。(3)重點(diǎn)分析引起PLL抖動的主要因素,闡述抖動的分類機(jī)制、抖動分解測試原理、探頭效應(yīng)等。通過對照實(shí)驗(yàn)、多次重復(fù)實(shí)驗(yàn)、控制變量法等測試方法,深入透徹地分析抖動來源及形成機(jī)理,并給出了降低外部抖動的測試方案,減小測試引入的誤差。(4)為了獲得高精度、高穩(wěn)定度的測試板,以便更加準(zhǔn)確地測試PLL的抖動指標(biāo),本文還對PLL測試板進(jìn)行了優(yōu)化設(shè)計,從電路設(shè)計、PCB設(shè)計及元器件選型等方面,詳細(xì)敘述了測試板開發(fā)的流程。最后應(yīng)用新設(shè)計的測試板進(jìn)行重復(fù)實(shí)驗(yàn),測試結(jié)果表明新測試板_V2.0在穩(wěn)定度方面大幅提升,外部噪聲明顯減小,能更加準(zhǔn)確地衡量PLL的抖動指標(biāo)。本文從PLL芯片測試背景、測試系統(tǒng)固化、測試標(biāo)準(zhǔn)統(tǒng)一、測試方法規(guī)范等角度,全面論述了PLL芯片測試的系統(tǒng)方法,對時鐘抖動的研究有極其重要的意義。
[Abstract]:As a clock chip, PLL is widely used in modern IC products such as wireless communication, consumer electronics and so on. Its functions include phase synchronization and clock frequency doubling. One of the key indexes to measure the performance of PLL is jitter (phase noise in frequency domain). In PLL chip testing, how to accurately measure the clock jitter of PLL has become an increasingly important issue. For the jitter evaluation of PLL, the circuit simulation in the design stage is far from enough. Only after the functional verification and reliability test of the finished chip behind the convection chip, can the design be finally determined whether the design is correct or not. In this paper, the testing principle and jitter factors of PLL chip are described in detail. The specific work is as follows: 1) expatiate the working principle of PLL, noise analysis and circuit level jitter analogue. Build the PLL test platform, analyze the physical meaning of jitter parameter. By using oscilloscope, phase noise meter, test board, data analysis software and other equipment to measure the index of entity chip, to verify the performance of PLL, to analyze the main factors that cause PLL jitter, and to expound the classification mechanism of jitter. Jitter decomposition test principle, probe effect and so on. In order to obtain high accuracy, the source and formation mechanism of jitter are thoroughly analyzed by means of control experiment, repeated experiment, control variable method and so on. The test scheme to reduce the external jitter is given, and the error introduced in the test is reduced. The test board with high stability is used to test the jitter index of PLL more accurately. This paper also optimizes the design of PLL test board, and describes the development process of the test board in detail from the aspects of circuit design, PCB design and components selection. The test results show that the stability of the new test board V2.0 is greatly improved, the external noise is obviously reduced, and the jitter index of PLL can be measured more accurately. From the point of view of PLL chip test background, test system solidification, uniform test standard and test method specification, this paper discusses the system method of PLL chip testing, which is of great significance to the research of clock jitter.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN911.8
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本文編號：1966817