發(fā)布時(shí)間：2018-04-21 22:17

  本文選題：極化碼 + QC-LDPC碼��； 參考：《南京航空航天大學(xué)》2014年碩士論文

【摘要】：自從Shannon定理被提出以來(lái),尋找性能能夠接近甚至達(dá)到Shannon極限的信道編碼一直是通信領(lǐng)域研究的熱點(diǎn)之一。極化碼是目前發(fā)現(xiàn)的性能最接近Shannon極限的一種信道編碼,它是由Arikan提出的。極化碼的優(yōu)越性能在理論上得到了嚴(yán)格的證明,但在實(shí)際應(yīng)用中還存在一些問(wèn)題,需要進(jìn)一步探索研究。而目前被廣泛使用的是LDPC碼,這是由Gallarger博士在1962年提出的一種信道編碼,但由于實(shí)際條件所限,直到90年代才被廣泛研究與應(yīng)用。由于LDPC碼具有非常好的性能,且實(shí)現(xiàn)方式簡(jiǎn)單高效,因此得到了廣泛的重視與研究,并且已經(jīng)成為第四代移動(dòng)通信、衛(wèi)星通信、網(wǎng)絡(luò)數(shù)據(jù)傳輸?shù)葟?qiáng)有力的競(jìng)爭(zhēng)者。QC-LDPC碼是LDPC碼的一個(gè)子類,由于具有準(zhǔn)循環(huán)特性,因此它的編碼與譯碼都可以用硬件高效實(shí)現(xiàn)。本文首先主要研究了信道的合并與拆分過(guò)程,然后基于此分析了信道的極化過(guò)程,并給出信道極化的示意圖,以及在高斯信道下進(jìn)行仿真得到的性能曲線�？梢钥闯鰳O化碼是基于信道極化過(guò)程傳輸信息的,且性能優(yōu)越。其次簡(jiǎn)單介紹了LDPC碼通用的編碼過(guò)程,并給出了針對(duì)QC-LDPC碼準(zhǔn)循環(huán)結(jié)構(gòu)的塊編碼過(guò)程。然后進(jìn)一步研究了QC—LDPC碼的隨機(jī)構(gòu)造過(guò)程,詳細(xì)介紹了消除4環(huán)與6環(huán)的過(guò)程。文章也給出了各自的性能比較,并構(gòu)造了一個(gè)本文硬件實(shí)現(xiàn)中的碼字。然后研究了LDPC碼的幾種軟判決譯碼算法,并對(duì)其譯碼的性能進(jìn)行了詳細(xì)的分析,給出了不同的軟件仿真結(jié)果對(duì)比,并確定了算法的修正因子。最終確定在硬件實(shí)現(xiàn)中采用基于歸一化算法的分層譯碼算法,并對(duì)其中所有的軟信息數(shù)據(jù)采用6bits量化處理。最后分析了LDPC碼譯碼器的多種結(jié)構(gòu),確定本文的設(shè)計(jì)中采用分層譯碼結(jié)構(gòu),并詳細(xì)介紹了各個(gè)子模塊的實(shí)現(xiàn)功能,然后運(yùn)用verilog硬件描述語(yǔ)言完成整個(gè)譯碼器的設(shè)計(jì)。使用Quartus軟件在Alter公司的EP3SL340H1152I4芯片上完成譯碼器的布局布線與綜合優(yōu)化,并調(diào)用Modelsim軟件完成譯碼器時(shí)序的仿真。在設(shè)定時(shí)鐘頻率為50MHZ,迭代5次的情況下,譯碼器達(dá)到了79.5Mbps的吞吐率。
[Abstract]:Since the Shannon theorem was proposed, it has been one of the hotspots in the field of communication to find channel coding that can reach or even reach the Shannon limit. Polarization code is one of the channel codes which is found to be the closest to the limit of Shannon. It is proposed by Arikan. The superior performance of polarization codes has been proved strictly in theory, but there are still some problems in practical applications, which need to be further explored. At present, LDPC codes are widely used, which was proposed by Dr. Gallarger in 1962. However, due to the limitation of practical conditions, it was not widely studied and applied until the 1990s. Because of its excellent performance and simple and efficient implementation, LDPC code has been paid more and more attention, and has become the fourth generation mobile communication and satellite communication. QC-LDPC code is a subclass of LDPC code, which is a strong competitor such as network data transmission. Because of its quasi-cyclic property, its coding and decoding can be implemented efficiently by hardware. In this paper, the process of channel merging and splitting is studied, then the polarization process of the channel is analyzed, and the schematic diagram of channel polarization and the performance curve obtained by simulation under Gao Si channel are given. It can be seen that the polarization code transmits information based on the channel polarization process, and its performance is superior. Secondly, the general coding process of LDPC codes is briefly introduced, and the block coding process for quasi-cyclic structure of QC-LDPC codes is given. Then the random construction process of QC-LDPC codes is studied, and the process of eliminating 4 rings and 6 rings is introduced in detail. This paper also gives a comparison of their performance and constructs a codeword in the hardware implementation of this paper. Then, several soft decision decoding algorithms for LDPC codes are studied, and their decoding performance is analyzed in detail. The results of different software simulations are compared, and the correction factors of the algorithms are determined. Finally, the hierarchical decoding algorithm based on normalization algorithm is adopted in hardware implementation, and all soft information data are processed by 6bits quantization. Finally, this paper analyzes the various structures of the LDPC decoder, determines that the layered decoding structure is adopted in the design of this paper, and introduces the implementation functions of each sub-module in detail. Then, the design of the decoder is completed by using the verilog hardware description language. The Quartus software is used to complete the layout, wiring and synthesis optimization of the decoder on the EP3SL340H1152I4 chip of Alter Company, and the time sequence simulation of the decoder is completed by using Modelsim software. When the clock frequency is 50 MHz and the iteration is 5 times, the decoder achieves the throughput of 79.5Mbps.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.22;TN791

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 孫葉;基于SC算法的Polar碼譯碼性能研究[D];西安電子科技大學(xué);2013年

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本文編號(hào)：1784311