發(fā)布時(shí)間：2018-04-06 07:21

  本文選題：時(shí)間數(shù)字轉(zhuǎn)換器游標(biāo)門控環(huán)形振蕩器　切入點(diǎn)：全數(shù)字鎖相環(huán)　出處：《復(fù)旦大學(xué)》2014年碩士論文

【摘要】：在射頻無(wú)線通信領(lǐng)域中,傳統(tǒng)的頻率綜合器基本上都是采用電荷泵鎖相環(huán)(Charge Pump Phase-Locked Loop)。低電壓深亞微米工藝的發(fā)展,給數(shù)字電路帶來(lái)了空前的集成度,卻使傳統(tǒng)射頻電路的實(shí)現(xiàn)更加復(fù)雜困難。近年來(lái),全數(shù)字鎖相環(huán)(All-Digital Phase-Locked Loop, ADPLL)由于可集成度高,可移植性好以及魯棒性成為了研究的熱點(diǎn)。時(shí)間數(shù)字轉(zhuǎn)換器(Time-to-Digital Converter, TDC)是ADPLL的關(guān)鍵模塊,TDC的分辨率決定著ADPLL的帶內(nèi)相位噪聲。本文的主要工作是研究設(shè)計(jì)了一種應(yīng)用于2.5-5GHz寬帶全數(shù)字鎖相環(huán)的門控游標(biāo)型時(shí)間數(shù)字轉(zhuǎn)換器。主要研究特色有：1)鎖相環(huán)在鎖定過程中和鎖定后對(duì)TDC測(cè)量范圍、分辨率的要求是不同的。鎖定過程中對(duì)測(cè)量范圍要求高,對(duì)分辨率要求低,鎖定后對(duì)測(cè)量范圍的要求低,對(duì)分辨率要求高。為了滿足鎖相環(huán)不同狀態(tài)對(duì)TDC測(cè)量范圍和分辨率的不同要求,所設(shè)計(jì)的TDC具有兩種量化模式——粗量化模式和細(xì)量化模式,模式判決電路能根據(jù)TDC輸入信號(hào)幅度的大小自動(dòng)選擇量化模式。2)由于鎖相環(huán)是分?jǐn)?shù)分頻的,在鎖定之后,不斷變化的分頻比會(huì)使TDC輸入信號(hào)的時(shí)間間隔增大。為了增加TDC細(xì)量化模式的測(cè)量范圍,使TDC在鎖相環(huán)鎖定后一直工作在細(xì)量化模式,TDC的量化單元采用了兩級(jí)量化結(jié)構(gòu)——第一級(jí)為1-bit decision-select,第二級(jí)為游標(biāo)門控環(huán)形振蕩器(Vernier gated-ring-oscillator, Vernier GRO)。3)在傳統(tǒng)的Vernier GRO中,采用SR觸發(fā)器做比較器制約了Vernier GRO的測(cè)量范圍和GRO設(shè)計(jì)的靈活性。本設(shè)計(jì)采用了一種新型結(jié)構(gòu)的相位比較器,消除了采用SR觸發(fā)器做比較器對(duì)測(cè)量范圍的制約,提高了GRO設(shè)計(jì)的靈活性。芯片采用TSMC 0.13μm工藝實(shí)現(xiàn),電源電壓為1.2V,測(cè)試結(jié)果表明,TDC的采樣頻率不低于40MHz,粗量化模式的測(cè)量范圍不小于25ns,細(xì)量化模式的測(cè)量范圍為1.8ns。應(yīng)用于ADPLL中,在3.68GHz頻率處,環(huán)路的帶內(nèi)相位噪聲為-92dBc/Hz@5kHz,對(duì)應(yīng)的TDC有效分辨率為23ps。
[Abstract]:In the field of RF wireless communication, the traditional frequency synthesizers are basically charge Pump Phase-Locked Loopers.The development of low-voltage deep submicron technology brings unprecedented integration to digital circuits, but it makes the realization of traditional RF circuits more complex and difficult.In recent years, All-Digital Phase-Locked Loop (ADPLL) has become a hotspot for its high integration, good portability and robustness.Time-to-digital converter (TDC) is a key module of ADPLL. The resolution of TDC determines the in-band phase noise of ADPLL.The main work of this paper is to study and design a gated Vernier time Digital Converter (TDC) for 2.5-5GHz wideband all-digital phase-locked loop (DPLL).The main research features are: (1) TDC measurement range and resolution requirements are different in the process of locking and after locking.In the process of locking, the requirement of measuring range is high, the requirement of resolution is low, the requirement of measurement range is low after locking, and the requirement of resolution is high.In order to meet the different requirements of TDC measurement range and resolution in different states of PLL, the designed TDC has two quantization modes: coarse quantization mode and fine quantization mode.The mode decision circuit can automatically select quantization mode. 2 according to the magnitude of the TDC input signal. Because the phase-locked loop is fractional frequency division, the time interval of the TDC input signal will be increased by changing frequency division ratio after locking.In order to increase the measurement range of the TDC fine quantization mode,The quantization unit that causes TDC to work in fine quantization mode after PLL locking adopts a two-level quantization structure-the first stage is 1-bit decision-selectand the second stage is Vernier gated-roscing-illator.3) in the traditional Vernier GRO, the Vernier gated-roscing-illator (Vernier GROT. 3) is the first level of quantization, and the second stage is Vernier gated-roscillator (Vernier. 3).Using SR flip-flop as comparator restricts the measurement range of Vernier GRO and the flexibility of GRO design.A new structure phase comparator is used in this design, which eliminates the restriction of measuring range by SR flip-flop and improves the flexibility of GRO design.The chip is realized by TSMC 0.13 渭 m technology and the power supply voltage is 1.2 V. the test results show that the sampling frequency is not less than 40MHz, the measurement range of coarse quantization mode is not less than 25ns, and the measurement range of fine quantization mode is 1.8ns.In ADPLL, the in-band phase noise of the loop is -92 dBc / Hz @ 5kHz at the 3.68GHz frequency, and the corresponding TDC effective resolution is 23ps.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.8

【參考文獻(xiàn)】

相關(guān)博士學(xué)位論文 前1條

1 陸平;應(yīng)用于寬帶數(shù)據(jù)通信的CMOS環(huán)振型頻率綜合器研究[D];復(fù)旦大學(xué);2007年

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本文編號(hào)：1718544