本文選題：電荷泵鎖相環(huán)頻率綜合器　切入點：鑒頻鑒相器　出處：《東南大學》2014年碩士論文

【摘要】：據不完全統(tǒng)計,人們所獲取的信息有80%以上是通過視覺器官得到的。隨著半導體技術的不斷提高,圖像傳感器因其能實現圖像信息的獲取、轉換和擴展,而得到越來越廣泛的應用。高集成度低功耗的互補金屬氧化物半導體圖像傳感器(CMOS Image Sensor, CIS)逐漸取代電荷耦合元件圖像傳感器(CCD Image Sensor, CCD)成為圖像傳感器的主流器件,電荷泵鎖相環(huán)頻率綜合器.(Charge Pump Phase Locked Loop frequency synthesizer, CPPLL)以其低功耗、高速、低抖動和低成本的優(yōu)勢在CIS中得到廣泛的應用,作為其中的關鍵模塊鑒頻鑒相器(Phase Frequency Detector, PFD)和電荷泵(Charge Pump, CP),前者決定了系統(tǒng)的精度和穩(wěn)定度,而后者為系統(tǒng)提供了寬的頻率捕捉范圍和快速的鎖定能力。本文首先介紹CP PLL的項目背景；然后分析了CP PLL的特點,闡述了CP PLL中關鍵模塊PFD以及CP的工作原理和結構分類；接著詳細討論了PFD和CP的設計指標以及設計中的難點問題,通過基于TSPC (True Single Phase Clock, TSPC)動態(tài)D觸發(fā)器式高精度PFD,以及結合寬輸入范圍誤差運放和自偏置共源共柵電流鏡結構的CP的設計,實現了電荷泵充放電流的高精度寬范圍匹配的設計要求;最后本文在0.13μm CMOS工藝下完成了PFD和CP模塊的版圖設計和優(yōu)化,并對電路進行了流片驗證。測試結果表明：在1.8V電源電壓下,PFD的各種邏輯功能均正確；CP在0.3V-1.7V的輸出電壓范圍內工作電流基本穩(wěn)定在100μA,在0.4V-1.7V的電壓范圍內,失配電流小于0.4μA,PFD和CP總的功耗為7.2mmW。作為圖像信息領域的一個研究熱點,開發(fā)與CIS相關的高性能PFD和CP芯片具有重要的研究價值和市場應用前景,本課題設計的PFD和CP已成功應用于CIS芯片中。
[Abstract]:According to incomplete statistics, more than 80% of the information obtained by people is obtained through visual organs. With the continuous improvement of semiconductor technology, image sensors can achieve the acquisition, conversion and expansion of image information. The complementary metal oxide semiconductor image sensor with high integration and low power consumption has gradually replaced the charge coupled element image sensor (CCD-CCD Image sensor) as the mainstream device of the image sensor. Charge Pump Phase Locked Loop frequency synthesizer (CPPLL) is widely used in CIS with its advantages of low power consumption, high speed, low jitter and low cost. As a key module, the phase Frequency detector (PFDs) and the charge pump charge pump (PFDs) determine the accuracy and stability of the system. The latter provides the system with wide frequency capture range and fast locking capability. Firstly, this paper introduces the project background of CP PLL, then analyzes the characteristics of CP PLL, and expounds the working principle and structure classification of the key module PFD and CP in CP PLL. Then, the design index of PFD and CP and the difficult problems in the design are discussed in detail. Based on TSPC true Single Phase lock (TSPC) dynamic D flip-flop high precision PFDs, and the design of CP with wide input range error operational amplifier and self-bias CSM structure, the design of CP-FDs based on dynamic D flip-flop is presented. The design requirements of charge pump charge-discharge flow with high precision and wide range matching are realized. Finally, the layout design and optimization of PFD and CP modules are completed in 0.13 渭 m CMOS process. The test results show that all logic functions of the circuit are correct at 1.8 V power supply voltage. The current working current is basically stable at 100 渭 A in the output voltage range of 0.3V-1.7V, and is within the voltage range of 0.4V-1.7V. The total power consumption of the mismatched current is less than 0.4 渭 An PFD and CP is 7.2 mmW. as a research hotspot in the field of image information, the development of high-performance PFD and CP chips related to CIS has important research value and market application prospect. The PFD and CP designed in this paper have been successfully applied to CIS chip.
【學位授予單位】：東南大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN911.8

【參考文獻】

相關期刊論文 前6條

1 石東新;傅新宇;張遠;;CMOS與CCD性能及高清應用比較[J];通信技術;2010年12期

2 倪景華;黃其煜;;CMOS圖像傳感器及其發(fā)展趨勢[J];光機電信息;2008年05期

3 司龍;胡貴才;熊元新;;一種新型的高性能鑒頻鑒相器[J];微電子學與計算機;2006年07期

4 劉曉燕;葉青;;CMOS電荷泵的結構設計與分析[J];科學技術與工程;2006年13期

5 彭穎,應建華,顏學超,李春霞;一種用于鎖相環(huán)的正反饋互補型電荷泵電路[J];華中科技大學學報(自然科學版);2005年02期

6 李桂華,孫仲林,吉利久;CMOS鎖相環(huán)PLL的設計研究[J];半導體雜志;2000年03期

，

本文編號：1680503