發(fā)布時間：2018-03-17 22:22

  本文選題：LDPC　切入點：加權(quán)比特翻轉(zhuǎn)算法　出處：《西北大學(xué)學(xué)報(自然科學(xué)版)》2014年06期 　論文類型：期刊論文

【摘要】：針對Euclidean Geometry(EG)-LDPC碼碼字的循環(huán)特性以及FWBF(fast weighted bit flipping)算法的算法結(jié)構(gòu)設(shè)計高速LDPC譯碼器。具體實現(xiàn)方法如下:首先通過對RAM進行合理的劃分,賦給不同的RAM相應(yīng)的規(guī)則號和初始地址值保證數(shù)據(jù)的無沖突存取,然后通過向量化操作實現(xiàn)運算數(shù)據(jù)的高速存取。此外,校驗式品質(zhì)計算模塊通過引入一種新型的樹形搜索電路來降低該模塊的功耗和延遲。最后,對EG255碼采用5路并行模式,在Cyclone III EP3C120F780C7芯片上實現(xiàn),信息吞吐量可達75.98Mbs,占用芯片邏輯資源不超過23%,RAM資源不超過4%。
[Abstract]:According to the cyclic characteristic of Euclidean Geometry(EG)-LDPC codeword and the algorithm structure of FWBF(fast weighted bit flippingalgorithm, a high speed LDPC decoder is designed. Assigned to different RAM corresponding rule numbers and initial address values to ensure non-conflict access to data, and then through vectorization operations to achieve high-speed access to operational data. A new type of tree search circuit is introduced to reduce the power consumption and delay of the module. Finally, the EG255 code is implemented on the Cyclone III EP3C120F780C7 chip in 5-channel parallel mode. The information throughput can reach 75.98 Mbsand the occupied chip logic resources are not more than 23 and RAM resources are not more than 4.
【作者單位】： 中國電子科技集團公司電子科學(xué)研究院;西安電子科技大學(xué)通信工程學(xué)院;
【基金】：國家自然科學(xué)基金資助項目(61072069) 教育部科學(xué)技術(shù)研究重點(重大)基金資助項目(2010ZX03002-005)
【分類號】：TN911.22
，

本文編號：1626753