本文選題：分時模數轉換器　切入點：失配誤差　出處：《電子科技大學》2014年碩士論文　論文類型：學位論文

【摘要】：數字信號處理技術是現(xiàn)代通信系統(tǒng)中不可或缺的關鍵,其中模擬數字轉化器(ADC)搭起了模擬世界到數字世界的橋梁。在現(xiàn)代的數字通信系統(tǒng)中,傳輸速率達Gbps,需要同時具有高精度、高采樣頻率特性的ADC完成采樣。由于單片ADC受工藝限制難以滿足要求,多通道的分時ADC結構就成為了替代的主流選擇之一。各通道間的不匹配會帶來較嚴重的失配誤差,從而對通信系統(tǒng)的整體性能造成不良影響。本文針對OFDM系統(tǒng),深入探討了分時ADC的幾種主要的失配誤差對系統(tǒng)性能的影響情況,并結合信道均衡方案對ADC失配誤差進行了聯(lián)合校準。論文主要包括以下內容:首先,針對分時ADC的時鐘、增益失配誤差對OFDM接收機造成的影響進行了系統(tǒng)建模,分析了子ADC數目對接收機性能的影響以及系統(tǒng)對ADC采樣精度的要求,并在此基礎上給出了失配誤差校準及信道均衡的聯(lián)合算法。通過合理地設計子ADC的數目,可以極大地簡化聯(lián)合算法的難度,從而使其具有可實現(xiàn)性。其次,復數矩陣求逆是聯(lián)合均衡算法硬件實現(xiàn)中的關鍵技術,本文從算法和實現(xiàn)兩個方面,研究了幾種常用的矩陣求逆算法(基于QR分解、Cholesky分解及基于伴隨矩陣求逆等),并對各算法的有效性、實現(xiàn)復雜度等多個方面進行了對比評估。最后,在RTL級上對聯(lián)合算法進行了電路設計與實現(xiàn),并在Xilinx Virtex-6上進行了實際測試,仿真與測試結果顯示,在10%失配誤差的情況下,經過聯(lián)合算法均衡后的OFDM系統(tǒng)BER從-210降到-410左右,電路的最高時鐘頻率可達251.2MHz。
[Abstract]:Digital signal processing technology is an indispensable key in modern communication system, in which the analog digital converter ADCbuilds the bridge between analog world and digital world. The transmission rate is up to GBPs, which requires the ADC with high precision and high sampling frequency to complete the sampling. Because the single chip ADC is limited by the process, it is difficult to meet the requirement. Multi-channel time-sharing ADC structure has become one of the mainstream alternatives. The mismatch between the channels will bring serious mismatch error, which will have a negative impact on the overall performance of the communication system. In this paper, the influence of several main mismatch errors of time-sharing ADC on the system performance is discussed, and the ADC mismatch error is calibrated by combining the channel equalization scheme. The main contents of this paper are as follows: first, aiming at the clock of time-sharing ADC, The effect of gain mismatch error on OFDM receiver is modeled. The influence of the number of sub-#en1# on receiver performance and the requirement of ADC sampling accuracy are analyzed. On this basis, the joint algorithm of mismatch error calibration and channel equalization is given. By reasonably designing the number of sub-#en0#, the difficulty of the joint algorithm can be greatly simplified and the algorithm is realizable. Inverse of complex matrix is the key technology in hardware implementation of joint equalization algorithm. In this paper, several common matrix inversion algorithms (Cholesky decomposition based on QR factorization and inverse algorithm based on adjoint matrix) are studied, and their effectiveness and implementation complexity are compared and evaluated. The circuit design and implementation of the joint algorithm are carried out on the RTL level, and the actual test is carried out on the Xilinx Virtex-6. The simulation and test results show that the BER of the OFDM system after the equalization of the joint algorithm is reduced from -210 to -410 under the condition of 10% mismatch error. The highest clock frequency of the circuit can reach 251.2 MHz.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN929.53

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本文編號：1623551