本文選題：功能驗(yàn)證　切入點(diǎn)：靜態(tài)時(shí)序分析　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著我國(guó)航天事業(yè)的不斷蓬勃發(fā)展,新型航天器所獲得的圖像數(shù)據(jù)量越來(lái)越大,這給星上數(shù)據(jù)存儲(chǔ)帶來(lái)了困難,也給傳輸信道造成繁重負(fù)擔(dān)。圖像壓縮系統(tǒng)作為星載數(shù)傳系統(tǒng)的重要組成部分,能有效的對(duì)數(shù)據(jù)進(jìn)行壓縮。采用高性能圖像壓縮芯片有利于系統(tǒng)的實(shí)現(xiàn),也有利于提高系統(tǒng)的穩(wěn)定性,同時(shí)使得系統(tǒng)具有實(shí)時(shí)壓縮圖像數(shù)據(jù)的能力。本課題組承擔(dān)的某型號(hào)高速圖像壓縮芯片以JPEG2000為核心算法,支持無(wú)損壓縮和有損壓縮,最高工作頻率為210MHz,最高處理速率大于105MSamples/s。該芯片采用了130nm工藝生產(chǎn),規(guī)模4千多萬(wàn)門(mén)。該圖像壓縮芯片具有高處理速率、低功耗、抗輻照等優(yōu)點(diǎn),為航天航空發(fā)展需要的專用元器件,符合我國(guó)航天航空器件高可靠高性能的要求。本論文主要研究了該芯片的驗(yàn)證測(cè)試工作,包括功能驗(yàn)證、靜態(tài)時(shí)序分析、時(shí)序仿真和單粒子效應(yīng)模擬實(shí)驗(yàn)。功能驗(yàn)證主要針對(duì)芯片壓縮核、外掛存儲(chǔ)器、配置接口、相機(jī)接口、碼流輸出接口、芯片工作頻率以及異步時(shí)序等展開(kāi)。不同的驗(yàn)證選取不同的針對(duì)性向量進(jìn)行測(cè)試。對(duì)于接口,以分析其接口時(shí)序?yàn)橹?保證其符合芯片接口規(guī)范。靜態(tài)時(shí)序分析通過(guò)PrimeTime抽取整個(gè)電路的所有同步時(shí)序路徑,根據(jù)路徑的門(mén)延時(shí)和線延時(shí)計(jì)算每條路徑的總延時(shí),最終得到了完整的靜態(tài)時(shí)序報(bào)告。根據(jù)靜態(tài)時(shí)序報(bào)告,分析和優(yōu)化存在時(shí)序違例的關(guān)鍵路徑。時(shí)序仿真使用網(wǎng)表與時(shí)序約束文件,通過(guò)時(shí)序仿真驗(yàn)證平臺(tái),完成了PLL工作時(shí)序、相機(jī)接口時(shí)序、碼流輸出接口時(shí)序、SDRAM接口時(shí)序、異步時(shí)序等驗(yàn)證工作。根據(jù)單粒子輻照實(shí)驗(yàn)要求,搭建了以FPGA為核心的自動(dòng)化測(cè)試平臺(tái),實(shí)現(xiàn)了自動(dòng)發(fā)送圖像、自動(dòng)比對(duì)、實(shí)時(shí)顯示以及實(shí)時(shí)存儲(chǔ)等功能。實(shí)驗(yàn)過(guò)程中使用多種粒子分別對(duì)兩塊芯片進(jìn)行了測(cè)試,實(shí)驗(yàn)結(jié)果顯示,一期芯片存在單粒子鎖定敏感的問(wèn)題,二期芯片由于采用了新的工藝,解決了單粒子鎖定的問(wèn)題。
[Abstract]:With the rapid development of the space industry in our country, the amount of image data obtained by the new spacecraft is increasing, which makes it difficult to store the data on board. As an important part of spaceborne data transmission system, image compression system can compress data effectively. Using high performance image compression chip is beneficial to the realization of the system. It is also helpful to improve the stability of the system and make the system have the ability to compress image data in real time. The core algorithm of a certain type of high-speed image compression chip is JPEG2000, which supports lossless compression and lossy compression. The highest working frequency is 210MHz, and the highest processing rate is more than 105MSamples / s. The chip is manufactured by 130nm process and has a scale of more than 4,000 gates. The image compression chip has the advantages of high processing rate, low power consumption, irradiating resistance and so on. The special components for aerospace development meet the requirements of high reliability and high performance of aerospace devices in China. This paper mainly studies the verification and testing work of this chip, including function verification, static timing analysis. Timing simulation and single particle effect simulation experiment. Function verification is mainly for chip compression core, external memory, configuration interface, camera interface, bitstream output interface, Chip frequency and asynchronous timing expansion. Different validation selected different targeted vectors for testing. For the interface, mainly to analyze its interface timing, The static timing analysis extracts all synchronous sequential paths of the whole circuit through PrimeTime, and calculates the total delay of each path according to the gate delay and line delay of the path. Finally, the complete static timing report is obtained. According to the static timing report, the critical path of timing violation is analyzed and optimized. The timing simulation uses the network table and timing constraint file, and completes the PLL working timing through the timing simulation verification platform. Camera interface timing, bitstream output interface timing, SDRAM interface timing, asynchronous timing, etc. According to the requirements of single particle irradiation experiment, an automatic test platform based on FPGA is built, which can automatically send images and compare them automatically. Real time display and real time storage are used to test the two chips. The experimental results show that the first stage chip has the problem of single particle locking sensitivity, and the second phase chip has adopted a new technology. The problem of single particle locking is solved.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：V557;TN919.81

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本文編號(hào)：1613757