本文選題：60GHz　切入點：毫米波　出處：《電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：60GHz通信在前幾年還是通信頻段的一塊空白,但隨著這幾年歐美日等國家相繼推出專屬于自己的60GHz通信頻段,60GHz通信正式開放使用,逐漸開始蓬勃發(fā)展起來。隨之英特爾、IBM等通信業(yè)巨頭相繼推出了應(yīng)用于無線通信的芯片,由此帶動了整個行業(yè)的發(fā)展。就目前態(tài)勢來看,受限于功耗和成本的要求,60GHz通信技術(shù)還未完全成熟,離正式商用還有很長一段距離。在很長一段時間,射頻前端芯片基本上都是用砷化鎵(GaAs)材料制作,這主要是基于GaAs工藝截止頻率高、噪聲和增益比較理想方面的考慮,但隨著無線通信的發(fā)展,對芯片的集成化和低功耗度提出了更高的要求。GaAs制作的芯片由于價格昂貴,已經(jīng)無法滿足大多數(shù)人的需求,而CMOS工藝以成本低、功耗低、易于集成、制備手段成熟等優(yōu)點,令其成為近幾年芯片業(yè)發(fā)展的主流。早期的CMOS工藝受限、截止頻率低,但隨著集成制作手段的提高,深亞微米級別的CMOS工藝越來越被人們所掌握,越來越多的芯片制造商把眼光投向了CMOS制作工藝上。本論文首先介紹了60GHz通信以及射頻集成發(fā)展的概況,然后對通信系統(tǒng)射頻前端的發(fā)射機和接收機結(jié)構(gòu)進行了分析。然后介紹了片上集成的代表性產(chǎn)品--Vubiq公司研制的60GHz頻段的通信開發(fā)系統(tǒng)。根據(jù)實際項目需要,考慮到成本和開發(fā)周期的問題,重點對混合集成方式構(gòu)建的前端系統(tǒng)進行仿真。挑選合適的器件搭建了60GHz的發(fā)射、接收通信系統(tǒng)鏈路,主要對搭建系統(tǒng)進行增益、選擇性、相位噪聲、噪聲系數(shù)、路徑衰減等方面的仿真和結(jié)果分析。本文后半段對60GHz低噪聲放大器射頻芯片(RFIC)進行分析與設(shè)計:首先根據(jù)指標(biāo)要求,分析了用于60GHz頻段的低噪聲放大器的拓?fù)浣Y(jié)構(gòu),從增益、噪聲系數(shù)、功耗三方面確定設(shè)計方案,接著用Cadence IC 5141集成電路設(shè)計軟件,分別在臺積電(TSMC)0.18μm和0.13μm RF CMOS工藝下,對不同的輸入匹配結(jié)構(gòu)進行仿真設(shè)計,最終在0.13μmRF CMOS工藝下設(shè)計出了一款工作在60GHz頻段、噪聲系數(shù)小于10dB、增益大于12dB、功耗小于100mW的低噪聲放大器。
[Abstract]:The 60GHz communication is still a blank in the communication frequency band in the past few years. However, with the introduction of 60GHz communication band which belongs to Europe, America and Japan and other countries in the past few years, the 60GHz communication band has been officially opened for use. Gradually began to flourish. With the Intel, IBM and other communications giants have introduced chips for wireless communications, which has led to the development of the entire industry. From the current situation, Limited by power consumption and cost requirements, 60GHz communication technology is not yet fully developed, and it is still a long way from commercial use. For a long time, RF front-end chips are basically made of GaAs (GaAs) materials. This is mainly based on the consideration of high cut-off frequency, noise and gain of GaAs process. However, with the development of wireless communication, the chip made by .GaAs is more expensive because of the higher requirement of chip integration and low power consumption. CMOS process has become the mainstream of chip industry development in recent years because of its advantages of low cost, low power consumption, easy integration, mature preparation methods, etc. The early CMOS process is limited, and the cut-off frequency is low. However, with the improvement of integrated manufacturing methods, the deep submicron CMOS process has been more and more mastered by people. More and more chip manufacturers are focusing on CMOS fabrication technology. This paper first introduces the development of 60GHz communication and RF integration. Then, the transmitter and receiver structure of RF front-end of communication system are analyzed. Then, the representative product of on-chip integration is introduced, which is a 60GHz communication development system developed by Vubiq Company. Considering the cost and the development cycle, the simulation of the front-end system constructed by the hybrid integration mode is emphasized. The appropriate device is selected to build the 60GHz transmission and receive communication system link, and the gain and selectivity of the built system are mainly carried out. Simulation and result analysis of phase noise, noise coefficient, path attenuation and so on. In the second half of this paper, the RF chip RFICs of 60GHz LNA are analyzed and designed. The topology of the low noise amplifier used in the 60GHz band is analyzed. The design scheme is determined from three aspects: gain, noise coefficient and power consumption. Then, the Cadence IC5141 integrated circuit design software is used in the TSMC 0.18 渭 m and 0.13 渭 m RF CMOS technology, respectively. Different input matching structures are simulated and designed. Finally, a low noise amplifier operating at 60GHz frequency band with noise coefficient less than 10 dB, gain greater than 12 dB and power consumption less than 100MW is designed under 0.13 渭 mRF CMOS process.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN928;TN722.3

【共引文獻】

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3 路小月;基于同步整流技術(shù)的高效DC-DC變換器芯片的設(shè)計[D];西安科技大學(xué);2012年

4 李萌;一種16位定點DSP核的設(shè)計與研究[D];沈陽工業(yè)大學(xué);2014年

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本文編號：1563967