本文關(guān)鍵詞： 全數(shù)字鎖相環(huán) 自適應(yīng) 比例積分控制 復(fù)合控制 FPGA　出處：《南華大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：本文研究了一種快速自適應(yīng)全數(shù)字鎖相環(huán)路，一方面，該系統(tǒng)采用了基于自適應(yīng)的比例積分控制策略，環(huán)路帶寬可以隨輸入信號(hào)頻率的大小進(jìn)行自動(dòng)調(diào)節(jié)，因而具有較大的鎖相范圍；另一方面，環(huán)路濾波器參數(shù)可以根據(jù)鑒相誤差的大小進(jìn)行快捕區(qū)、緩沖區(qū)和鎖定區(qū)的切換，即環(huán)路帶寬可以隨鑒相誤差的大小進(jìn)行自動(dòng)調(diào)節(jié)，有效的克服了環(huán)路捕捉速度和抗噪聲性能之間的矛盾。環(huán)路參數(shù)的實(shí)現(xiàn)則采用了數(shù)字移位相加的設(shè)計(jì)方法，較之傳統(tǒng)采用除法器的實(shí)現(xiàn)方法，大大的簡(jiǎn)化了電路結(jié)構(gòu)。整個(gè)鎖相環(huán)均由數(shù)字模塊構(gòu)成，克服了模擬鎖相環(huán)所固有的壓控振蕩器非線性、鑒相不精確、器件易飽和以及高階不穩(wěn)定等缺陷，使系統(tǒng)本身又具有參數(shù)穩(wěn)定、可靠性高和易于集成等特點(diǎn)。 在深入研究該鎖相環(huán)理論模型和和實(shí)現(xiàn)結(jié)構(gòu)的基礎(chǔ)上，最終通過(guò)自頂向下的模塊化設(shè)計(jì)技術(shù)對(duì)整個(gè)系統(tǒng)進(jìn)行了電路設(shè)計(jì)，在QuartusII軟件環(huán)境下進(jìn)行了相關(guān)的綜合仿真，并比較分析了該設(shè)計(jì)在不同環(huán)路控制參數(shù)作用下的各項(xiàng)性能，最后將設(shè)計(jì)程序下載到Altera公司的EP1C6Q240C8FPGA器件予以硬件實(shí)現(xiàn)。系統(tǒng)仿真與實(shí)測(cè)結(jié)果表明：采用自適應(yīng)控制與動(dòng)態(tài)比例積分控制相結(jié)合的復(fù)合控制方式，可使環(huán)路帶寬隨輸入信號(hào)頻率和鑒相誤差的變化進(jìn)行實(shí)時(shí)調(diào)節(jié)。當(dāng)系統(tǒng)時(shí)鐘為60MHz時(shí)，環(huán)路調(diào)節(jié)時(shí)間約為8個(gè)輸入信號(hào)周期，超調(diào)量為4.32%，，跟蹤鎖定范圍為40Hz-1MHz，系統(tǒng)各項(xiàng)性能和理論分析非常吻合。
[Abstract]:In this paper, a fast adaptive all-digital phase-locked loop is studied. On the one hand, the system adopts an adaptive proportional integral control strategy, and the loop bandwidth can be automatically adjusted with the input signal frequency. On the other hand, the parameters of the loop filter can be quickly captured according to the size of the phase discrimination error, and the switching between the buffer zone and the locking area, that is, the bandwidth of the loop can be automatically adjusted with the size of the phase discrimination error. The contradiction between the speed of the loop capture and the anti-noise performance is overcome effectively. The design method of digital shift and addition is used to realize the parameters of the loop, which is compared with the traditional implementation method of divider. The circuit structure is greatly simplified. The whole PLL is composed of digital modules, which overcomes the inherent defects of the analog PLL, such as nonlinear voltage controlled oscillator, inaccurate phase identification, easy saturation of devices and high order instability, etc. The system has the characteristics of stable parameters, high reliability and easy integration. On the basis of deeply studying the theoretical model and the realization structure of the PLL, the circuit design of the whole system is carried out through the top-down modular design technology, and the related comprehensive simulation is carried out under the environment of QuartusII software. The performances of the design under the action of different loop control parameters are compared and analyzed. Finally, the design program is downloaded to the EP1C6Q240C8FPGA device of Altera Company for hardware implementation. The system simulation and measured results show that the combination of adaptive control and dynamic proportional integral control is adopted. The loop bandwidth can be adjusted in real time with the change of input signal frequency and phase discrimination error. When the system clock is 60MHz, the loop adjusting time is about 8 input signal cycles. The overshoot is 4.32 and the tracking locking range is 40Hz-1MHz. The performance of the system is in good agreement with the theoretical analysis.
【學(xué)位授予單位】：南華大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN911.8

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