發(fā)布時(shí)間：2018-02-23 20:34

  本文關(guān)鍵詞： FPGA IDEA算法 對(duì)稱密碼算法 分組密碼　出處：《山東大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著通信與計(jì)算機(jī)技術(shù)的飛速發(fā)展,信息的存儲(chǔ)方式及傳輸方式發(fā)生了巨大的變化,越來(lái)越多的信息以數(shù)字化存在并由計(jì)算機(jī)通過網(wǎng)絡(luò)來(lái)傳遞,信息的安全問題引起了人們極大的重視。密碼算法成為信息安全問題的核心,算法的整體安全性也日益成為研究信息安全問題的關(guān)鍵。信息的快速發(fā)展推動(dòng)了密碼技術(shù)的發(fā)展,加密算法層出不窮。對(duì)稱密碼算法成為當(dāng)前密碼技術(shù)研究領(lǐng)域中的重要內(nèi)容之一,與其他密碼技術(shù)相比其保護(hù)數(shù)據(jù)在存儲(chǔ)與傳輸過程的安全性是無(wú)可替代的。AES算法的誕生使得分組密碼算法重新吸引了人們的眼球,登上了密碼研究的“大舞臺(tái)”。本文研究的主要課題就是圍繞分組密碼體制中的重要算法-IDEA加密算法進(jìn)行探討與分析。本文采用FPGA技術(shù)對(duì)一種對(duì)稱密碼體制即IDEA算法的加、解密模塊進(jìn)行了完整設(shè)計(jì)。首先對(duì)IDEA算法進(jìn)行總體的學(xué)習(xí)與了解,基于此算法的基本工作原理對(duì)其加密、解密兩個(gè)過程分別進(jìn)行了詳細(xì)的分析。根據(jù)IDEA加、解密算法的流程,采用8級(jí)流水線技術(shù)及自上而下的設(shè)計(jì)方法將該密碼芯片分模塊進(jìn)行設(shè)計(jì)并仿真。其中,密鑰生成模塊負(fù)責(zé)將原始密鑰轉(zhuǎn)化為算法所需要的子密鑰并進(jìn)行存儲(chǔ)操作；控制模塊是根據(jù)狀態(tài)的變化產(chǎn)生相應(yīng)的控制信號(hào)；運(yùn)算模塊主要實(shí)現(xiàn)輪結(jié)構(gòu),完成各種迭代運(yùn)算,同時(shí)解決了IDEA算法中一些復(fù)雜的運(yùn)算的硬件電路的實(shí)現(xiàn)問題。最后將各個(gè)模塊整合到一起進(jìn)行仿真綜合及驗(yàn)證給出系統(tǒng)的RTL級(jí)電路圖、綜合報(bào)告等。結(jié)果表明,該算法能夠準(zhǔn)確的在FPGA芯片上以1.4Gbps的速度實(shí)現(xiàn)加密及解密運(yùn)算,證明了IDEA硬件的可行性。
[Abstract]:With the rapid development of communication and computer technology, great changes have taken place in the storage and transmission of information. More and more information exists in digital form and is transmitted by computer through network. The problem of information security has aroused great attention. Cryptographic algorithms have become the core of information security problems, and the overall security of algorithms has become the key to the study of information security. The rapid development of information has promoted the development of cryptography technology. The algorithm of symmetric cryptography has become one of the most important contents in the field of cryptography. Compared with other cryptographic techniques, the security of data protection in the process of storage and transmission is irreplaceable. The birth of the. AES algorithm makes the block cipher algorithm attract people's attention again. The main research topic of this paper is to discuss and analyze the important algorithm in block cipher system-idea encryption algorithm. In this paper, we adopt FPGA technology to add a symmetric cipher system, that is, IDEA algorithm. The decryption module is designed completely. Firstly, the IDEA algorithm is studied and understood. Based on the basic working principle of this algorithm, the two processes of encryption and decryption are analyzed in detail. According to the flow of IDEA encryption and decryption algorithm, The cipher chip is designed and simulated by the 8-level pipeline technology and top-down design method, in which the key generation module is responsible for converting the original key into the sub-key needed by the algorithm and storing it. The control module produces the corresponding control signal according to the change of the state, and the operation module mainly realizes the wheel structure and completes various iterative operations. At the same time, the problem of hardware circuit realization of some complex arithmetic in IDEA algorithm is solved. Finally, the various modules are integrated together for simulation and synthesis, and the RTL circuit diagram and synthesis report of the system are given. The results show that, The algorithm can accurately implement encryption and decryption operation at 1.4 Gbps on FPGA chip, which proves the feasibility of IDEA hardware.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791;TN918.4

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 劉峰山;;基于FPGA的高速IDEA加密芯片電路結(jié)構(gòu)設(shè)計(jì)[J];科技信息;2010年27期

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本文編號(hào)：1527520